From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1755124AbcGHMGU (ORCPT ); Fri, 8 Jul 2016 08:06:20 -0400 Received: from terminus.zytor.com ([198.137.202.10]:52202 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755093AbcGHMGM (ORCPT ); Fri, 8 Jul 2016 08:06:12 -0400 Date: Fri, 8 Jul 2016 05:04:40 -0700 From: tip-bot for Andy Shevchenko Message-ID: Cc: hpa@zytor.com, andriy.shevchenko@linux.intel.com, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@kernel.org, bhelgaas@google.com Reply-To: bhelgaas@google.com, mingo@kernel.org, torvalds@linux-foundation.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, peterz@infradead.org, hpa@zytor.com, andriy.shevchenko@linux.intel.com In-Reply-To: <1467749348-100518-2-git-send-email-andriy.shevchenko@linux.intel.com> References: <1467749348-100518-2-git-send-email-andriy.shevchenko@linux.intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:x86/platform] x86/platform/intel-mid: Extend PWRMU to support Penwell Git-Commit-ID: ca22312dc840065206285626829ceed8bb4df88c X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: ca22312dc840065206285626829ceed8bb4df88c Gitweb: http://git.kernel.org/tip/ca22312dc840065206285626829ceed8bb4df88c Author: Andy Shevchenko AuthorDate: Tue, 5 Jul 2016 23:09:08 +0300 Committer: Ingo Molnar CommitDate: Fri, 8 Jul 2016 11:00:06 +0200 x86/platform/intel-mid: Extend PWRMU to support Penwell Intel Penwell is one of the first SoCs in Intel MID series. It has slightly older version of PWRMU IP, though it is compatible with one found on Intel Tangier. Since we are not using (yet) any advanced stuff in the driver we may safely re-use what it's done for Intel Tangier for now. Extend PWRMU driver to support Intel Penwell by adding PCI ID and re-using existing ->set_initial_state() function. Signed-off-by: Andy Shevchenko Cc: Bjorn Helgaas Cc: Linus Torvalds Cc: Peter Zijlstra Cc: Thomas Gleixner Link: http://lkml.kernel.org/r/1467749348-100518-2-git-send-email-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar --- arch/x86/platform/intel-mid/pwr.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/arch/x86/platform/intel-mid/pwr.c b/arch/x86/platform/intel-mid/pwr.c index 59faf05..5bc90dd 100644 --- a/arch/x86/platform/intel-mid/pwr.c +++ b/arch/x86/platform/intel-mid/pwr.c @@ -75,6 +75,7 @@ #define LSS_PWS_BITS 2 /* power state width */ /* Supported device IDs */ +#define PCI_DEVICE_ID_PENWELL 0x0828 #define PCI_DEVICE_ID_TANGIER 0x11a1 struct mid_pwr_dev { @@ -354,7 +355,7 @@ static int mid_pwr_probe(struct pci_dev *pdev, const struct pci_device_id *id) return 0; } -static int tng_set_initial_state(struct mid_pwr *pwr) +static int mid_set_initial_state(struct mid_pwr *pwr) { unsigned int i, j; int ret; @@ -397,12 +398,13 @@ static int tng_set_initial_state(struct mid_pwr *pwr) return 0; } -static const struct mid_pwr_device_info tng_info = { - .set_initial_state = tng_set_initial_state, +static const struct mid_pwr_device_info mid_info = { + .set_initial_state = mid_set_initial_state, }; static const struct pci_device_id mid_pwr_pci_ids[] = { - { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&tng_info }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PENWELL), (kernel_ulong_t)&mid_info }, + { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_TANGIER), (kernel_ulong_t)&mid_info }, {} }; MODULE_DEVICE_TABLE(pci, mid_pwr_pci_ids);