From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757051AbcEEJtd (ORCPT ); Thu, 5 May 2016 05:49:33 -0400 Received: from terminus.zytor.com ([198.137.202.10]:44788 "EHLO terminus.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756499AbcEEJtb (ORCPT ); Thu, 5 May 2016 05:49:31 -0400 Date: Thu, 5 May 2016 02:48:24 -0700 From: tip-bot for Alexander Shishkin Message-ID: Cc: linux-kernel@vger.kernel.org, peterz@infradead.org, eranian@google.com, mathieu.poirier@linaro.org, bp@alien8.de, vincent.weaver@maine.edu, acme@redhat.com, alexander.shishkin@linux.intel.com, torvalds@linux-foundation.org, hpa@zytor.com, tglx@linutronix.de, mingo@kernel.org, acme@infradead.org, jolsa@redhat.com Reply-To: acme@infradead.org, jolsa@redhat.com, hpa@zytor.com, torvalds@linux-foundation.org, alexander.shishkin@linux.intel.com, tglx@linutronix.de, mingo@kernel.org, bp@alien8.de, acme@redhat.com, vincent.weaver@maine.edu, linux-kernel@vger.kernel.org, mathieu.poirier@linaro.org, eranian@google.com, peterz@infradead.org In-Reply-To: <1461857746-31346-4-git-send-email-alexander.shishkin@linux.intel.com> References: <1461857746-31346-4-git-send-email-alexander.shishkin@linux.intel.com> To: linux-tip-commits@vger.kernel.org Subject: [tip:perf/core] perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it Git-Commit-ID: ccbebba4c6bfda8e3ef9e431ce2c3d91c5fc5a63 X-Mailer: tip-git-log-daemon Robot-ID: Robot-Unsubscribe: Contact to get blacklisted from these emails MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset=UTF-8 Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Commit-ID: ccbebba4c6bfda8e3ef9e431ce2c3d91c5fc5a63 Gitweb: http://git.kernel.org/tip/ccbebba4c6bfda8e3ef9e431ce2c3d91c5fc5a63 Author: Alexander Shishkin AuthorDate: Thu, 28 Apr 2016 18:35:46 +0300 Committer: Ingo Molnar CommitDate: Thu, 5 May 2016 10:16:28 +0200 perf/x86/intel/pt: Bypass PT vs. LBR exclusivity if the core supports it Not all cores prevent using Intel PT and LBRs simultaneously, although most of them still do as of today. This patch adds an opt-in flag for such cores to disable mutual exclusivity between PT and LBR; also flip it on for Goldmont. Signed-off-by: Alexander Shishkin Signed-off-by: Peter Zijlstra (Intel) Cc: Arnaldo Carvalho de Melo Cc: Arnaldo Carvalho de Melo Cc: Borislav Petkov Cc: Jiri Olsa Cc: Linus Torvalds Cc: Mathieu Poirier Cc: Peter Zijlstra Cc: Stephane Eranian Cc: Thomas Gleixner Cc: Vince Weaver Cc: vince@deater.net Link: http://lkml.kernel.org/r/1461857746-31346-4-git-send-email-alexander.shishkin@linux.intel.com Signed-off-by: Ingo Molnar --- arch/x86/events/core.c | 6 ++++++ arch/x86/events/intel/core.c | 1 + arch/x86/events/perf_event.h | 1 + 3 files changed, 8 insertions(+) diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c index 41d93d0..5e5e76a 100644 --- a/arch/x86/events/core.c +++ b/arch/x86/events/core.c @@ -360,6 +360,9 @@ int x86_add_exclusive(unsigned int what) { int i; + if (x86_pmu.lbr_pt_coexist) + return 0; + if (!atomic_inc_not_zero(&x86_pmu.lbr_exclusive[what])) { mutex_lock(&pmc_reserve_mutex); for (i = 0; i < ARRAY_SIZE(x86_pmu.lbr_exclusive); i++) { @@ -380,6 +383,9 @@ fail_unlock: void x86_del_exclusive(unsigned int what) { + if (x86_pmu.lbr_pt_coexist) + return; + atomic_dec(&x86_pmu.lbr_exclusive[what]); atomic_dec(&active_events); } diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index 90ba3ae..cd31940 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -3609,6 +3609,7 @@ __init int intel_pmu_init(void) */ x86_pmu.pebs_aliases = NULL; x86_pmu.pebs_prec_dist = true; + x86_pmu.lbr_pt_coexist = true; x86_pmu.flags |= PMU_FL_HAS_RSP_1; pr_cont("Goldmont events, "); break; diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h index 7d62a02..8bd764d 100644 --- a/arch/x86/events/perf_event.h +++ b/arch/x86/events/perf_event.h @@ -601,6 +601,7 @@ struct x86_pmu { u64 lbr_sel_mask; /* LBR_SELECT valid bits */ const int *lbr_sel_map; /* lbr_select mappings */ bool lbr_double_abort; /* duplicated lbr aborts */ + bool lbr_pt_coexist; /* LBR may coexist with PT */ /* * Intel PT/LBR/BTS are exclusive