From: tip-bot for Cyrill Gorcunov <gorcunov@openvz.org>
To: linux-tip-commits@vger.kernel.org
Cc: linux-kernel@vger.kernel.org, hpa@zytor.com, mingo@redhat.com,
gorcunov@openvz.org, a.p.zijlstra@chello.nl, fweisbec@gmail.com,
ming.m.lin@intel.com, tglx@linutronix.de, mingo@elte.hu
Subject: [tip:perf/core] perf, x86: P4 PMU -- add missing bit in CCCR mask
Date: Wed, 19 May 2010 07:57:47 GMT [thread overview]
Message-ID: <tip-ce7f15452cc1dc1eca795542367871a07f37aa79@git.kernel.org> (raw)
In-Reply-To: <20100518212439.354345151@openvz.org>
Commit-ID: ce7f15452cc1dc1eca795542367871a07f37aa79
Gitweb: http://git.kernel.org/tip/ce7f15452cc1dc1eca795542367871a07f37aa79
Author: Cyrill Gorcunov <gorcunov@openvz.org>
AuthorDate: Wed, 19 May 2010 01:19:19 +0400
Committer: Ingo Molnar <mingo@elte.hu>
CommitDate: Wed, 19 May 2010 09:41:06 +0200
perf, x86: P4 PMU -- add missing bit in CCCR mask
Should be there for the sake of RAW events.
Signed-off-by: Cyrill Gorcunov <gorcunov@openvz.org>
CC: Lin Ming <ming.m.lin@intel.com>
CC: Peter Zijlstra <a.p.zijlstra@chello.nl>
CC: Frederic Weisbecker <fweisbec@gmail.com>
LKML-Reference: <20100518212439.354345151@openvz.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
---
arch/x86/include/asm/perf_event_p4.h | 3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/arch/x86/include/asm/perf_event_p4.h b/arch/x86/include/asm/perf_event_p4.h
index b05400a..64a8ebf 100644
--- a/arch/x86/include/asm/perf_event_p4.h
+++ b/arch/x86/include/asm/perf_event_p4.h
@@ -89,7 +89,8 @@
P4_CCCR_ENABLE)
/* HT mask */
-#define P4_CCCR_MASK_HT (P4_CCCR_MASK | P4_CCCR_THREAD_ANY)
+#define P4_CCCR_MASK_HT \
+ (P4_CCCR_MASK | P4_CCCR_OVF_PMI_T1 | P4_CCCR_THREAD_ANY)
#define P4_GEN_ESCR_EMASK(class, name, bit) \
class##__##name = ((1 << bit) << P4_ESCR_EVENTMASK_SHIFT)
next prev parent reply other threads:[~2010-05-19 7:58 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-05-18 21:19 [patch 0/4] [perf -tip/master] p4 pmu updates Cyrill Gorcunov
2010-05-18 21:19 ` [patch 1/4] x86,perf: P4 PMU -- do a real check for ESCR address being in hash Cyrill Gorcunov
2010-05-19 7:57 ` [tip:perf/core] perf, x86: " tip-bot for Cyrill Gorcunov
2010-05-18 21:19 ` [patch 2/4] x86,perf: p4_pmu_schedule_events -- use smp_processor_id instead of raw_ Cyrill Gorcunov
2010-05-19 7:57 ` [tip:perf/core] perf, x86: P4_pmu_schedule_events " tip-bot for Cyrill Gorcunov
2010-05-18 21:19 ` [patch 3/4] x86,perf: P4 PMU -- add missing bit in CCCR mask Cyrill Gorcunov
2010-05-19 7:57 ` tip-bot for Cyrill Gorcunov [this message]
2010-05-18 21:19 ` [patch 4/4] x86,perf: P4 PMU -- prepare header for user-space inclusion Cyrill Gorcunov
2010-05-19 7:35 ` Ingo Molnar
2010-05-19 7:41 ` Cyrill Gorcunov
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