From: tip-bot for Harish Chegondi <tipbot@zytor.com>
To: linux-tip-commits@vger.kernel.org
Cc: acme@redhat.com, lukasz.anaczkowski@intel.com,
tglx@linutronix.de, peterz@infradead.org, eranian@google.com,
hpa@zytor.com, harish.chegondi@intel.com, mingo@kernel.org,
andi.kleen@intel.com, jolsa@redhat.com,
harish.chegondi@gmail.com, vincent.weaver@maine.edu,
torvalds@linux-foundation.org, kan.liang@intel.com,
linux-kernel@vger.kernel.org
Subject: [tip:perf/core] perf/x86/intel/uncore: Remove hard coding of PMON box control MSR offset
Date: Wed, 6 Jan 2016 10:53:56 -0800 [thread overview]
Message-ID: <tip-dae25530a44ad9e6523495ebc8b37bb0a1640490@git.kernel.org> (raw)
In-Reply-To: <872e8ef16cfc38e5ff3b45fac1094e6f1722e4ad.1449470704.git.harish.chegondi@intel.com>
Commit-ID: dae25530a44ad9e6523495ebc8b37bb0a1640490
Gitweb: http://git.kernel.org/tip/dae25530a44ad9e6523495ebc8b37bb0a1640490
Author: Harish Chegondi <harish.chegondi@intel.com>
AuthorDate: Mon, 7 Dec 2015 14:32:31 -0800
Committer: Ingo Molnar <mingo@kernel.org>
CommitDate: Wed, 6 Jan 2016 11:15:37 +0100
perf/x86/intel/uncore: Remove hard coding of PMON box control MSR offset
Call uncore_pci_box_ctl() function to get the PMON box control MSR offset
instead of hard coding the offset. This would allow us to use this
snbep_uncore_pci_init_box() function for other PCI PMON devices whose box
control MSR offset is different from SNBEP_PCI_PMON_BOX_CTL.
Signed-off-by: Harish Chegondi <harish.chegondi@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Andi Kleen <andi.kleen@intel.com>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Harish Chegondi <harish.chegondi@gmail.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Kan Liang <kan.liang@intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Lukasz Anaczkowski <lukasz.anaczkowski@intel.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://lkml.kernel.org/r/872e8ef16cfc38e5ff3b45fac1094e6f1722e4ad.1449470704.git.harish.chegondi@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
index f2ddfcc..bfb9656 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_uncore_snbep.c
@@ -315,8 +315,9 @@ static u64 snbep_uncore_pci_read_counter(struct intel_uncore_box *box, struct pe
static void snbep_uncore_pci_init_box(struct intel_uncore_box *box)
{
struct pci_dev *pdev = box->pci_dev;
+ int box_ctl = uncore_pci_box_ctl(box);
- pci_write_config_dword(pdev, SNBEP_PCI_PMON_BOX_CTL, SNBEP_PMON_BOX_CTL_INT);
+ pci_write_config_dword(pdev, box_ctl, SNBEP_PMON_BOX_CTL_INT);
}
static void snbep_uncore_msr_disable_box(struct intel_uncore_box *box)
prev parent reply other threads:[~2016-01-06 18:54 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2015-12-07 22:32 [PATCH 1/2] perf/x86/intel/uncore: Remove hard coding of PMON box control MSR offset Harish Chegondi
2015-12-07 22:32 ` [PATCH 2/2] perf/x86/intel/uncore: Add Knights Landing uncore PMU support Harish Chegondi
2015-12-08 9:07 ` Peter Zijlstra
2015-12-09 21:03 ` Harish Chegondi
2015-12-09 23:37 ` Peter Zijlstra
2015-12-09 23:43 ` Harish Chegondi
2016-01-06 18:54 ` [tip:perf/core] " tip-bot for Harish Chegondi
2016-01-06 18:53 ` tip-bot for Harish Chegondi [this message]
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