Re: [tip:perfcounters/core] perf_counter: x86: Fix call-chain support to use NMI-safe methods

Ingo Molnar
2009-06-15T18:46:22Z

* H. Peter Anvin <hpa@zytor.com> wrote:

> Ingo Molnar wrote:
> > * Mathieu Desnoyers <mathieu.desnoyers@polymtl.ca> wrote:
> >
> >> Hrm, would it be possible to save the c2 register upon nmi handler
> >> entry and restore it before iret instead ? This would ensure a
> >> nmi-interrupted page fault handler would continue what it was
> >> doing with a non-corrupted cr2 register after returning from nmi.
> >>
> >> Plus, this involves no modification to the page fault handler fast
> >> path.
> >
> > I guess this kind of nesting would work too - assuming the cr2 can
> > be written to robustly.
> >
> > And i suspect CPU makers pull off a few tricks to stage the cr2 info
> > away from the page fault entry execution asynchronously, so i'd not
> > be surprised if writing to it uncovered unknown-so-far side-effects
> > in CPU implementations.
> >
>
> I wouldn't actually expect that, *as long as* there is
> serialization between the cr2 write and the cr2 read.

Well, is there any OS that heavily relies on cr2 writes and which
uses them from NMI context, and which CPU makers care about?
(Meaning: Windows, pretty much.)

If not then i agree that in theory it should work fine, but in
practice we only know that we dont know the unknown risk here ;-)

Ingo