Re: [PATCH v2 0/2] staging: rtl8723au: core: endianness issues

[Jes Sorensen <Jes.Sorensen@redhat.com>]

David Decotigny <ddecotig@gmail.com> writes:
> The code shows a couple inconsistencies (described in commit
> descriptions) which would not be an issue on little-endian cpus, but
> could cause breakage on non-LE cpus. Note: I could not test on real
> hardware, these patches created based on sparse reports.
>
> Hostory:
>   - resending the same patches to correct recipients, only changed
>     commit descriptions (credits to Dan Carpenter)
>
> ############################################
> # Patch Set Summary:
>
> David Decotigny (2):
>   staging: rtl8723au: core: avoid bitwise arithmetic with forced
>     endianness
>   staging: rtl8723au: core: remove redundant endianness conversion
>
>  drivers/staging/rtl8723au/core/rtw_mlme_ext.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)

Looks fine to me, however if you fiddle with this same value twice,
wouldn't it be better to do it in one patch?

Cheers,
Jes