Re: [patch V4 14/36] rseq: Cache CPU ID and MM CID values

Mathieu Desnoyers
2025-09-09T15:01:10Z

On 2025-09-09 10:13, Thomas Gleixner wrote:
> On Tue, Sep 09 2025 at 09:43, Mathieu Desnoyers wrote:
>> On 2025-09-08 17:31, Thomas Gleixner wrote:
>>> /**
>>> + * struct rseq_ids - Cache for ids, which need to be updated
>>
>> need -> needs
>
> ids is plural, so 'need' is correct, no?

It's the cache that needs to be updated (cache for ids). So
technically the verb conjugates with "cache" (singular) and not
"ids".

>
>>> + * @cpu_cid: Compound of @cpu_id and @mm_cid to make the
>>> + * compiler emit a single compare on 64-bit
>>> + * @cpu_id: The CPU ID which was written last to user space
>>> + * @mm_cid: The MM CID which was written last to user space
>>> + *
>>> + * @cpu_id and @mm_cid are updated when the data is written to user space.
>>> + */
>>> +struct rseq_ids {
>>> + union {
>>> + u64 cpu_cid;
>>> + struct {
>>> + u32 cpu_id;
>>> + u32 mm_cid;
>>> + };
>>> + };
>>> +};
>>> +
>>> +/**
>>> * struct rseq_data - Storage for all rseq related data
>>> * @usrptr: Pointer to the registered user space RSEQ memory
>>> * @len: Length of the RSEQ region
>>> * @sig: Signature of critial section abort IPs
>>> * @event: Storage for event management
>>> + * @ids: Storage for cached CPU ID and MM CID
>>
>> It's far from clear from the diff, but is there a missing space at the
>> beginning of the line above ?
>
> No. The actual diff is:
>
> * @event: Storage for event management
> + * @ids: Storage for cached CPU ID and MM CID
> */
>
> It's just the reply quoting which makes it ugly.

Sounds good.

Thanks,

Mathieu

>

--
Mathieu Desnoyers
EfficiOS Inc.