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[103.168.172.201]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6cb3b66b0cdsm5407156d6.80.2024.09.26.21.29.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Sep 2024 21:29:37 -0700 (PDT) Received: from phl-compute-05.internal (phl-compute-05.phl.internal [10.202.2.45]) by mailfauth.phl.internal (Postfix) with ESMTP id 587AF1200043; Fri, 27 Sep 2024 00:29:36 -0400 (EDT) Received: from phl-mailfrontend-01 ([10.202.2.162]) by phl-compute-05.internal (MEProxy); Fri, 27 Sep 2024 00:29:36 -0400 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeftddrvddtkedgkedvucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdggtfgfnhhsuhgsshgtrhhisggvpdfu rfetoffkrfgpnffqhgenuceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnh htshculddquddttddmnecujfgurhepfffhvfevuffkfhggtggujgesthdtredttddtvden ucfhrhhomhepuehoqhhunhcuhfgvnhhguceosghoqhhunhdrfhgvnhhgsehgmhgrihhlrd gtohhmqeenucggtffrrghtthgvrhhnpeegfeefvdevffejueekjeduleduveehgfehleek gffgueeuvdeuteejhfehledtueenucffohhmrghinhepghhouggsohhlthdrohhrghdpvg hffhhitghiohhsrdgtohhmnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehm rghilhhfrhhomhepsghoqhhunhdomhgvshhmthhprghuthhhphgvrhhsohhnrghlihhthi dqieelvdeghedtieegqddujeejkeehheehvddqsghoqhhunhdrfhgvnhhgpeepghhmrghi lhdrtghomhesfhhigihmvgdrnhgrmhgvpdhnsggprhgtphhtthhopedvjedpmhhouggvpe hsmhhtphhouhhtpdhrtghpthhtohepmhgrthhhihgvuhdruggvshhnohihvghrshesvghf fhhitghiohhsrdgtohhmpdhrtghpthhtohepthhorhhvrghlughssehlihhnuhigqdhfoh hunhgurghtihhonhdrohhrghdprhgtphhtthhopehjohhnrghsrdhosggvrhhhrghushgv rheshhhurgifvghitghlohhuugdrtghomhdprhgtphhtthhopehlihhnuhigqdhkvghrnh gvlhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehrtghusehvghgvrhdr khgvrhhnvghlrdhorhhgpdhrtghpthhtoheplhhinhhugidqmhhmsehkvhgrtghkrdhorh hgpdhrtghpthhtoheplhhkmhhmsehlihhsthhsrdhlihhnuhigrdguvghvpdhrtghpthht ohepphgruhhlmhgtkheskhgvrhhnvghlrdhorhhgpdhrtghpthhtohepfhhrvgguvghrih gtsehkvghrnhgvlhdrohhrgh X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 27 Sep 2024 00:29:35 -0400 (EDT) Date: Thu, 26 Sep 2024 21:28:48 -0700 From: Boqun Feng To: Mathieu Desnoyers , Linus Torvalds Cc: Jonas Oberhauser , linux-kernel@vger.kernel.org, rcu@vger.kernel.org, linux-mm@kvack.org, lkmm@lists.linux.dev, "Paul E. McKenney" , Frederic Weisbecker , Neeraj Upadhyay , Joel Fernandes , Josh Triplett , "Uladzislau Rezki (Sony)" , rostedt , Lai Jiangshan , Zqiang , Peter Zijlstra , Ingo Molnar , Will Deacon , Waiman Long , Mark Rutland , Thomas Gleixner , Kent Overstreet , Vlastimil Babka , maged.michael@gmail.com, Neeraj Upadhyay Subject: Re: [RFC PATCH 1/4] hazptr: Add initial implementation of hazard pointers Message-ID: References: <48992c9f-6c61-4716-977c-66e946adb399@efficios.com> <2b2aea37-06fe-40cb-8458-9408406ebda6@efficios.com> <55633835-242c-4d7f-875b-24b16f17939c@huaweicloud.com> <54487a36-f74c-46c3-aed7-fc86eaaa9ca2@huaweicloud.com> <0b262fe5-2fc5-478d-bf66-f208723238d5@efficios.com> Precedence: bulk X-Mailing-List: lkmm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Fri, Sep 27, 2024 at 09:37:50AM +0800, Boqun Feng wrote: > > > On Fri, Sep 27, 2024, at 9:30 AM, Mathieu Desnoyers wrote: > > On 2024-09-27 02:01, Boqun Feng wrote: > >> #define ADDRESS_EQ(var, expr) \ > >> ({ \ > >> bool _____cmp_res = (unsigned long)(var) == (unsigned long)(expr); \ > >> \ > >> OPTIMIZER_HIDE_VAR(var); \ > >> _____cmp_res; \ > >> }) > > > > If the goal is to ensure gcc uses the register populated by the > > second, I'm afraid it does not work. AFAIU, "hiding" the dependency > > chain does not prevent the SSA GVN optimization from combining the Note it's not hiding the dependency, rather the equality, > > registers as being one and choosing one arbitrary source. "hiding" after OPTIMIZER_HIDE_VAR(var), compiler doesn't know whether 'var' is equal to 'expr' anymore, because OPTIMIZER_HIDE_VAR(var) uses "=r"(var) to indicate the output is overwritten. So when 'var' is referred later, compiler cannot use the register for a 'expr' value or any other register that has the same value, because 'var' may have a different value from the compiler's POV. > > the dependency chain before or after the comparison won't help here. > > > > int fct_hide_var_compare(void) > > { > > int *a, *b; > > > > do { > > a = READ_ONCE(p); > > asm volatile ("" : : : "memory"); > > b = READ_ONCE(p); > > } while (!ADDRESS_EQ(a, b)); > > Note that ADDRESS_EQ() only hide first parameter, so this should be ADDRESS_EQ(b, a). > I replaced ADDRESS_EQ(a, b) with ADDRESS_EQ(b, a), and the compile result shows it can prevent the issue: gcc 14.2 x86-64: fct_hide_var_compare: .L2: mov rcx, QWORD PTR p[rip] mov rdx, QWORD PTR p[rip] mov rax, rdx cmp rcx, rdx jne .L2 mov eax, DWORD PTR [rax] ret gcc 14.2.0 ARM64: fct_hide_var_compare: adrp x2, p add x2, x2, :lo12:p .L2: ldr x3, [x2] ldr x1, [x2] mov x0, x1 cmp x3, x1 bne .L2 ldr w0, [x0] ret Link to godbolt: https://godbolt.org/z/a7jsfzjxY Regards, Boqun > Regards, > Boqun > > > return *b; > > } > > > > gcc 14.2 x86-64: > > > > fct_hide_var_compare: > > mov rax,QWORD PTR [rip+0x0] # 67 > > mov rdx,QWORD PTR [rip+0x0] # 6e > > cmp rax,rdx > > jne 60 > > mov eax,DWORD PTR [rax] > > ret > > main: > > xor eax,eax > > ret > > > > gcc 14.2.0 ARM64: > > > > fct_hide_var_compare: > > adrp x0, .LANCHOR0 > > add x0, x0, :lo12:.LANCHOR0 > > .L12: > > ldr x1, [x0] > > ldr x2, [x0] > > cmp x1, x2 > > bne .L12 > > ldr w0, [x1] > > ret > > p: > > .zero 8 > > > > > > -- > > Mathieu Desnoyers > > EfficiOS Inc. > > https://www.efficios.com >