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McKenney" , Greg Kroah-Hartman , Linus Torvalds , Thomas Gleixner Subject: Re: [PATCH v5 03/10] rust: sync: atomic: Add ordering annotation types Message-ID: References: <20250618164934.19817-1-boqun.feng@gmail.com> <20250618164934.19817-4-boqun.feng@gmail.com> <20250619103155.GD1613376@noisy.programming.kicks-ass.net> <20250619143214.GJ1613376@noisy.programming.kicks-ass.net> Precedence: bulk X-Mailing-List: lkmm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250619143214.GJ1613376@noisy.programming.kicks-ass.net> On Thu, Jun 19, 2025 at 04:32:14PM +0200, Peter Zijlstra wrote: > On Thu, Jun 19, 2025 at 06:29:29AM -0700, Boqun Feng wrote: > > On Thu, Jun 19, 2025 at 12:31:55PM +0200, Peter Zijlstra wrote: > > > On Wed, Jun 18, 2025 at 09:49:27AM -0700, Boqun Feng wrote: > > > > > > > +//! Memory orderings. > > > > +//! > > > > +//! The semantics of these orderings follows the [`LKMM`] definitions and rules. > > > > +//! > > > > +//! - [`Acquire`] and [`Release`] are similar to their counterpart in Rust memory model. > > > > > > So I've no clue what the Rust memory model states, and I'm assuming > > > it is very similar to the C11 model. I have also forgotten what LKMM > > > states :/ > > > > > > Do they all agree on what RELEASE+ACQUIRE makes? > > > > > > > I think the question is irrelevant here, because we are implementing > > LKMM atomics in Rust using primitives from C, so no C11/Rust memory > > model in the picture for kernel Rust. > > The question is relevant in so far that the comment refers to them; and > if their behaviour is different in any way, this is confusing. > I did use the word "similar" and before that I said "The semantics of these orderings follows the [`LKMM`] definitions and rules." The referring was merely to avoid repeating the part like: - [`Acquire`] orders the load part of the operation against all following memory operations. - [`Release`] orders the store part of the operation against all preceding memory operations. because of this part, both models agree. But if you think this way is better, I could change it. > > But I think they do. I assume you mostly ask whether RELEASE(a) + > > ACQUIRE(b) (i.e. release and acquire on different variables) makes a TSO > > barrier [1]? We don't make it a TSO barrier in LKMM either (only > > unlock(a)+lock(b) is a TSO barrier) and neither does C11/Rust memory > > model. > > > > [1]: https://lore.kernel.org/lkml/20211202005053.3131071-1-paulmck@kernel.org/ > > Right, that! > > So given we build locks from atomics, this has to come from somewhere. > > The simplest lock -- TAS -- is: rmw.acquire + store.release. > > So while plain store.release + load.acquire might not make TSO (although > IIRC ARM added variants that do just that in an effort to aid x86 > emulation); store.release + rmw.acquire must, otherwise we cannot > satisfy that unlock+lock. > Make sense, so something like this in the model should work: diff --git a/tools/memory-model/linux-kernel.cat b/tools/memory-model/linux-kernel.cat index d7e7bf13c831..90cb6db6e335 100644 --- a/tools/memory-model/linux-kernel.cat +++ b/tools/memory-model/linux-kernel.cat @@ -27,7 +27,7 @@ include "lock.cat" (* Release Acquire *) let acq-po = [Acquire] ; po ; [M] let po-rel = [M] ; po ; [Release] -let po-unlock-lock-po = po ; [UL] ; (po|rf) ; [LKR] ; po +let po-unlock-lock-po = po ; (([UL] ; (po|rf) ; [LKR]) | ([Release]; (po;rf); [Acquire & RMW])) ; po (* Fences *) let R4rmb = R \ Noreturn (* Reads for which rmb works *) although I'm not sure whether there will be actual users that use this ordering. Regards, Boqun