From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from wnew2-smtp.messagingengine.com (wnew2-smtp.messagingengine.com [64.147.123.27]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21066291D for ; Thu, 22 Sep 2022 10:53:01 +0000 (UTC) Received: from compute3.internal (compute3.nyi.internal [10.202.2.43]) by mailnew.west.internal (Postfix) with ESMTP id C28772B059A3; Thu, 22 Sep 2022 06:52:59 -0400 (EDT) Received: from imap51 ([10.202.2.101]) by compute3.internal (MEProxy); Thu, 22 Sep 2022 06:53:00 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=arndb.de; h=cc :cc:content-type:date:date:from:from:in-reply-to:in-reply-to :message-id:mime-version:references:reply-to:sender:subject :subject:to:to; s=fm1; t=1663843979; x=1663847579; bh=cSRj8m6//S 4nzmuhOOEsOKmR8Il0fc1BoRQKLeM0xek=; b=dz6wqdl4kZMoMtAMLClFD0INx0 7BAEmvn72swpQTyghCbvkZB4LYJNkruxi/ppf7Lrwgm8vb1W4+LbllC1KGbzaWY2 PE86tTzsN1ewHNSHAymcLdhaw+XwGN7gTNvXvjN87lYMHQ1DemnYCPdWivehLCbz 87RaN5hSObbN1oarfbyiJS8/4NxFy1MrrtZ0T12r3H5x8TRNGZzOIh5rnp1xat+G Xl3FCpDrl5swixCJG1iWh23LQPyurL9bPPo2xbFHYN6VdrC7euXNngVQ7jrNBYoP e927ZI2w4ox5WspWtg5lSPjMKWzIoeP18UMNfiDGldIIU7MswNZN8xo7tqlQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= messagingengine.com; h=cc:cc:content-type:date:date:feedback-id :feedback-id:from:from:in-reply-to:in-reply-to:message-id :mime-version:references:reply-to:sender:subject:subject:to:to :x-me-proxy:x-me-proxy:x-me-sender:x-me-sender:x-sasl-enc; s= fm2; t=1663843979; x=1663847579; bh=cSRj8m6//S4nzmuhOOEsOKmR8Il0 fc1BoRQKLeM0xek=; b=R3d+pTy37CMSCYZ3dpdDqVRJxPO0PC54qMOr35F2FIbl yPTw1pLoLZn57bz9vTy2+rpBenU3LvxYfvL/Ve8fNz1nEosK0wBntg0XNS9/V/6d uhxPOBJv8IMxSArMS2SB+uhTbaulBzhAOKo1t7D4L6KgP1+aKRI6kh80zamNE4s4 saBPddd42SmNnq+FrpLbPGaeA/IoPgXHMI5u+ThXFeOjKMRBezQ2htdUNDyiYLal BLq1ZSJwtzwoh/uDUCy2wU0Wi8pOZT9mRP3EUspE/AS13Igz3EzpDD+tQIriHk4x uLSHCIEwIYDbf1dUxsOM1Ert01YC5XFJn0dDyvSCBQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedvfedrfeeffedgfedtucetufdoteggodetrfdotf fvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfqfgfvpdfurfetoffkrfgpnffqhgen uceurghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmne cujfgurhepofgfggfkjghffffhvfevufgtsehttdertderredtnecuhfhrohhmpedftehr nhguuceuvghrghhmrghnnhdfuceorghrnhgusegrrhhnuggsrdguvgeqnecuggftrfgrth htvghrnhepffehueegteeihfegtefhjefgtdeugfegjeelheejueethfefgeeghfektdek teffnecuvehluhhsthgvrhfuihiivgeptdenucfrrghrrghmpehmrghilhhfrhhomheprg hrnhgusegrrhhnuggsrdguvg X-ME-Proxy: Feedback-ID: i56a14606:Fastmail Received: by mailuser.nyi.internal (Postfix, from userid 501) id 68050B60086; Thu, 22 Sep 2022 06:52:58 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.7.0-alpha0-935-ge4ccd4c47b-fm-20220914.001-ge4ccd4c4 Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Message-Id: <01210adb-ff77-4ec5-8d10-ab56ae986d58@www.fastmail.com> In-Reply-To: <20220922113613.4d7273c8@xps-13> References: <202209210641.MziHAbW7-lkp@intel.com> <20220921104002.226ff3f6@xps-13> <7074197c-aa8d-f763-cb0f-03ea5335b923@sequans.com> <20220921164720.6bbc56d5@xps-13> <20220921183807.241e2518@xps-13> <6b5a2b19-39c6-5116-60c2-d292ae2e7bae@sequans.com> <20220922113613.4d7273c8@xps-13> Date: Thu, 22 Sep 2022 12:52:36 +0200 From: "Arnd Bergmann" To: "Miquel Raynal" , "Valentin Korenblit" Cc: "kernel test robot" , llvm@lists.linux.dev, kbuild-all@lists.01.org, linux-kernel@vger.kernel.org Subject: Re: [mtd:nand/next 11/31] drivers/mtd/nand/raw/cadence-nand-controller.c:1893:4: error: implicit declaration of function 'ioread64_rep' is invalid in C99 Content-Type: text/plain On Thu, Sep 22, 2022, at 11:36 AM, Miquel Raynal wrote: > vkorenblit@sequans.com wrote on Thu, 22 Sep 2022 10:18:46 +0200: >> >> Correct, this was my initial idea. However, this driver should work >> with every architecture or do we limit the scope to arm/arm64/x86_64? > > The driver should work on ARM and aarch64, I'm not aware of other > architectures with this IP. > > The driver should compile when COMPILE_TEST=y. It should also be written in a way that makes it plausible to use elsewhere. Since this is just a licensed IP core, there is a good chance that someone reused it on mips or riscv, or anything else. >> >> I believe what Valentin wanted to achieve in the first place, was to >> >> use 64-bit accesses when relevant (otherwise it does not work). >> > The width is read from a device specific register at >> > runtime, it is not related to the architecture you are >> > running on, presumably this is hardwired during the >> > design of an SoC, based on the capabilities of the DMA >> > engine: > > Well, yes, but in the mean time 64-bit DMA width will never be > used on 32-bit platforms. Why? Most architectures (including x86 and arm) allow you to run a 32-bit kernel on a 64-bit SoC. While this is almost always a bad idea to actually do, a driver should be written to work correctly in this setup. >> > This usually means the largest access that is valid for >> > reading from the FIFO, but usually smaller accesses work >> > as well, just slower. > > Mmh, ok, that's interesting, thanks for the pointer. > > But in the mean time I am only half satisfied, because we plan to do > twice more accesses than needed _just_ because of a the COMPILE_TEST > constraint. In my example, I had an #ifdef so it would only fall back to 32-bit accesses on the 64-bit register when running an actual 32-bit kernel, but leaving the 64-bit case efficient. Arnd