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From: kernel test robot <lkp@intel.com>
To: Min Li <min.li.xe@renesas.com>
Cc: llvm@lists.linux.dev, kbuild-all@lists.01.org,
	linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org
Subject: drivers/ptp/ptp_clockmatrix.c:1679: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
Date: Wed, 10 Nov 2021 15:29:13 +0800	[thread overview]
Message-ID: <202111101503.TWRXwHj0-lkp@intel.com> (raw)

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tree:   https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git master
head:   cb690f5238d71f543f4ce874aa59237cf53a877c
commit: da9facf1c1825201956c2553e06d455dea3e0313 ptp: ptp_clockmatrix: Add support for pll_mode=0 and manual ref switch of WF and WP
date:   8 weeks ago
config: i386-randconfig-a001-20211109 (attached as .config)
compiler: clang version 14.0.0 (https://github.com/llvm/llvm-project f3798ad5fa845771846599f3c088016e3aef800c)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=da9facf1c1825201956c2553e06d455dea3e0313
        git remote add linus https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
        git fetch --no-tags linus master
        git checkout da9facf1c1825201956c2553e06d455dea3e0313
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/ptp/ptp_clockmatrix.c:1679: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
    * Maximum absolute value for write phase offset in picoseconds


vim +1679 drivers/ptp/ptp_clockmatrix.c

  1677	
  1678	/**
> 1679	 * Maximum absolute value for write phase offset in picoseconds
  1680	 *
  1681	 * @channel:  channel
  1682	 * @delta_ns: delta in nanoseconds
  1683	 *
  1684	 * Destination signed register is 32-bit register in resolution of 50ps
  1685	 *
  1686	 * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
  1687	 */
  1688	static int _idtcm_adjphase(struct idtcm_channel *channel, s32 delta_ns)
  1689	{
  1690		struct idtcm *idtcm = channel->idtcm;
  1691		int err;
  1692		u8 i;
  1693		u8 buf[4] = {0};
  1694		s32 phase_50ps;
  1695		s64 offset_ps;
  1696	
  1697		if (channel->mode != PTP_PLL_MODE_WRITE_PHASE) {
  1698			err = channel->configure_write_phase(channel);
  1699			if (err)
  1700				return err;
  1701		}
  1702	
  1703		offset_ps = (s64)delta_ns * 1000;
  1704	
  1705		/*
  1706		 * Check for 32-bit signed max * 50:
  1707		 *
  1708		 * 0x7fffffff * 50 =  2147483647 * 50 = 107374182350
  1709		 */
  1710		if (offset_ps > MAX_ABS_WRITE_PHASE_PICOSECONDS)
  1711			offset_ps = MAX_ABS_WRITE_PHASE_PICOSECONDS;
  1712		else if (offset_ps < -MAX_ABS_WRITE_PHASE_PICOSECONDS)
  1713			offset_ps = -MAX_ABS_WRITE_PHASE_PICOSECONDS;
  1714	
  1715		phase_50ps = div_s64(offset_ps, 50);
  1716	
  1717		for (i = 0; i < 4; i++) {
  1718			buf[i] = phase_50ps & 0xff;
  1719			phase_50ps >>= 8;
  1720		}
  1721	
  1722		err = idtcm_write(idtcm, channel->dpll_phase, DPLL_WR_PHASE,
  1723				  buf, sizeof(buf));
  1724	
  1725		return err;
  1726	}
  1727	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

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                 reply	other threads:[~2021-11-10  7:29 UTC|newest]

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