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charset=us-ascii Content-Disposition: inline User-Agent: Mutt/1.10.1 (2018-07-13) tree: https://github.com/esmil/linux visionfive head: 4d0bf74de3a2e2bb05b6c110d3b258d005430d7f commit: 44b4542801a3eef74aee528fcb2799afc57e5c82 [50/54] RISC-V: Enable SIFIVE_L2_FLUSH for StarFive SoCs config: riscv-randconfig-c006-20220414 (https://download.01.org/0day-ci/archive/20220415/202204152012.W0cYA1eA-lkp@intel.com/config) compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 6b7e6ea489f6dd45a9b0da9ac20871560917b9b0) reproduce (this is a W=1 build): wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross chmod +x ~/bin/make.cross # install riscv cross compiling tool for clang build # apt-get install binutils-riscv64-linux-gnu # https://github.com/esmil/linux/commit/44b4542801a3eef74aee528fcb2799afc57e5c82 git remote add esmil https://github.com/esmil/linux git fetch --no-tags esmil visionfive git checkout 44b4542801a3eef74aee528fcb2799afc57e5c82 # save the config file to linux build tree mkdir build_dir COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=riscv SHELL=/bin/bash If you fix the issue, kindly add following tag as appropriate Reported-by: kernel test robot All errors (new ones prefixed by >>): >> drivers/soc/sifive/sifive_l2_cache.c:158:3: error: implicit declaration of function 'writeq' is invalid in C99 [-Werror,-Wimplicit-function-declaration] writeq(line, l2_base + SIFIVE_L2_FLUSH64); ^ drivers/soc/sifive/sifive_l2_cache.c:148:19: warning: result of comparison of constant 36507222016 with expression of type 'unsigned long' is always false [-Wtautological-constant-out-of-range-compare] (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + ~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 1 warning and 1 error generated. vim +/writeq +158 drivers/soc/sifive/sifive_l2_cache.c a967a289f16969 arch/riscv/mm/sifive_l2_cache.c Yash Shah 2019-05-06 126 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 127 #ifdef CONFIG_SIFIVE_L2_FLUSH 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 128 void sifive_l2_flush64_range(unsigned long start, unsigned long len) 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 129 { 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 130 unsigned long line; 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 131 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 132 if(!l2_base) { 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 133 pr_warn("L2CACHE: base addr invalid, skipping flush\n"); 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 134 return; 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 135 } 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 136 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 137 /* TODO: if (len == 0), skipping flush or going on? */ 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 138 if(!len) { 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 139 pr_debug("L2CACHE: flush64 range @ 0x%lx(len:0)\n", start); 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 140 return; 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 141 } 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 142 170da5f236a1d7 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 143 len = len + (start % SIFIVE_L2_FLUSH64_LINE_LEN); 170da5f236a1d7 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 144 start = ALIGN_DOWN(start, SIFIVE_L2_FLUSH64_LINE_LEN); 170da5f236a1d7 drivers/soc/sifive/sifive_l2_cache.c Atish Patra 2021-06-12 145 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 146 /* make sure the address is in the range */ 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 147 if(start < CONFIG_SIFIVE_L2_FLUSH_START || 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 148 (start + len) > (CONFIG_SIFIVE_L2_FLUSH_START + 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 149 CONFIG_SIFIVE_L2_FLUSH_SIZE)) { 56e0bd5b6b12ff drivers/soc/sifive/sifive_l2_cache.c Geert Uytterhoeven 2021-05-21 150 WARN(1, "L2CACHE: flush64 out of range: %lx(%lx), skip flush\n", 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 151 start, len); 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 152 return; 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 153 } 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 154 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 155 mb(); /* sync */ 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 156 for (line = start; line < start + len; 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 157 line += SIFIVE_L2_FLUSH64_LINE_LEN) { 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 @158 writeq(line, l2_base + SIFIVE_L2_FLUSH64); 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 159 mb(); 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 160 } 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 161 } 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 162 EXPORT_SYMBOL_GPL(sifive_l2_flush64_range); 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 163 #endif 704151e7f415c4 drivers/soc/sifive/sifive_l2_cache.c Tom 2021-01-08 164 :::::: The code at line 158 was first introduced by commit :::::: 704151e7f415c483a9c1854a8a0952f4f365c45d sifive/sifive_l2_cache: Add sifive_l2_flush64_range function :::::: TO: Tom :::::: CC: Emil Renner Berthing -- 0-DAY CI Kernel Test Service https://01.org/lkp