Re: [PATCH v23 06/10] soc: mediatek: add cmdq support of mtk-mmsys config API for mt8195 vdosys1

CK Hu
2022-06-22T03:10:09Z

Hi, Nancy:

On Mon, 2022-06-20 at 17:17 +0800, Nancy.Lin wrote:
> Add cmdq support for mtk-mmsys config API.
> The mmsys config register settings need to take effect with the other
> HW settings(like OVL_ADAPTOR...) at the same vblanking time.
>
> If we use CPU to write the mmsys reg, we can't guarantee all the
> settings can be written in the same vblanking time.
> Cmdq is used for this purpose. We prepare all the related HW settings
> in one cmdq packet. The first command in the packet is "wait stream
> done",
> and then following with all the HW settings. After the cmdq packet is
> flush to GCE HW. The GCE waits for the "stream done event" to coming
> and then starts flushing all the HW settings. This can guarantee all
> the settings flush in the same vblanking.

Reviewed-by: CK Hu <ck.hu@mediatek.com>

>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Tested-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
> ---
> drivers/soc/mediatek/mtk-mmsys.c | 54 +++++++++++++++++++-----
> --
> include/linux/soc/mediatek/mtk-mmsys.h | 15 +++++--
> 2 files changed, 50 insertions(+), 19 deletions(-)
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c
> b/drivers/soc/mediatek/mtk-mmsys.c
> index 48d5e5d1d0a1..999be064103b 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -178,6 +178,7 @@ struct mtk_mmsys {
> spinlock_t lock; /* protects mmsys_sw_rst_b reg */
> struct reset_controller_dev rcdev;
> phys_addr_t io_start;
> + struct cmdq_client_reg cmdq_base;
> };
>
> static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
> @@ -192,10 +193,24 @@ static int mtk_mmsys_find_match_drvdata(struct
> mtk_mmsys *mmsys,
> return -EINVAL;
> }
>
> -static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32
> offset, u32 mask, u32 val)
> +static void mtk_mmsys_update_bits(struct mtk_mmsys *mmsys, u32
> offset, u32 mask, u32 val,
> + struct cmdq_pkt *cmdq_pkt)
> {
> u32 tmp;
>
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + if (cmdq_pkt) {
> + if (mmsys->cmdq_base.size == 0) {
> + pr_err("mmsys lose gce property, failed to
> update mmsys bits with cmdq");
> + return;
> + }
> + cmdq_pkt_write_mask(cmdq_pkt, mmsys->cmdq_base.subsys,
> + mmsys->cmdq_base.offset + offset,
> val,
> + mask);
> + return;
> + }
> +#endif
> +
> tmp = readl_relaxed(mmsys->regs + offset);
> tmp = (tmp & ~mask) | val;
> writel_relaxed(tmp, mmsys->regs + offset);
> @@ -212,7 +227,7 @@ void mtk_mmsys_ddp_connect(struct device *dev,
> for (i = 0; i < mmsys->data->num_routes; i++)
> if (cur == routes[i].from_comp && next ==
> routes[i].to_comp)
> mtk_mmsys_update_bits(mmsys, routes[i].addr,
> routes[i].mask,
> - routes[i].val);
> + routes[i].val, NULL);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_connect);
>
> @@ -226,42 +241,45 @@ void mtk_mmsys_ddp_disconnect(struct device
> *dev,
>
> for (i = 0; i < mmsys->data->num_routes; i++)
> if (cur == routes[i].from_comp && next ==
> routes[i].to_comp)
> - mtk_mmsys_update_bits(mmsys, routes[i].addr,
> routes[i].mask, 0);
> + mtk_mmsys_update_bits(mmsys, routes[i].addr,
> routes[i].mask, 0, NULL);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> -void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> width, int height)
> +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> width, int height,
> + struct cmdq_pkt *cmdq_pkt)
> {
> mtk_mmsys_update_bits(dev_get_drvdata(dev),
> MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
> - ~0, height << 16 | width);
> + ~0, height << 16 | width, cmdq_pkt);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
>
> -void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int
> be_height)
> +void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int
> be_height,
> + struct cmdq_pkt *cmdq_pkt)
> {
> mtk_mmsys_update_bits(dev_get_drvdata(dev),
> MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
> - be_height << 16 | be_width);
> + be_height << 16 | be_width, cmdq_pkt);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_confing);
>
> void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool
> alpha_sel, u16 alpha,
> - u8 mode, u32 biwidth)
> + u8 mode, u32 biwidth, struct cmdq_pkt
> *cmdq_pkt)
> {
> struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
>
> mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx
> - 1) * 4, ~0,
> - alpha << 16 | alpha);
> + alpha << 16 | alpha, cmdq_pkt);
> mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 +
> idx),
> - alpha_sel << (19 + idx));
> + alpha_sel << (19 + idx), cmdq_pkt);
> mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx -
> 1) * 4,
> - GENMASK(31, 16) | GENMASK(1, 0), biwidth
> << 16 | mode);
> + GENMASK(31, 16) | GENMASK(1, 0), biwidth
> << 16 | mode, cmdq_pkt);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
>
> -void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> bool channel_swap)
> +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> bool channel_swap,
> + struct cmdq_pkt *cmdq_pkt)
> {
> mtk_mmsys_update_bits(dev_get_drvdata(dev),
> MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
> - BIT(4), channel_swap << 4);
> + BIT(4), channel_swap << 4, cmdq_pkt);
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
>
> @@ -274,9 +292,9 @@ static int mtk_mmsys_reset_update(struct
> reset_controller_dev *rcdev, unsigned l
> spin_lock_irqsave(&mmsys->lock, flags);
>
> if (assert)
> - mtk_mmsys_update_bits(mmsys, mmsys->data-
> >sw0_rst_offset, BIT(id), 0);
> + mtk_mmsys_update_bits(mmsys, mmsys->data-
> >sw0_rst_offset, BIT(id), 0, NULL);
> else
> - mtk_mmsys_update_bits(mmsys, mmsys->data-
> >sw0_rst_offset, BIT(id), BIT(id));
> + mtk_mmsys_update_bits(mmsys, mmsys->data-
> >sw0_rst_offset, BIT(id), BIT(id), NULL);
>
> spin_unlock_irqrestore(&mmsys->lock, flags);
>
> @@ -366,6 +384,12 @@ static int mtk_mmsys_probe(struct
> platform_device *pdev)
> mmsys->data = match_data->drv_data[0];
> }
>
> +#if IS_REACHABLE(CONFIG_MTK_CMDQ)
> + ret = cmdq_dev_get_client_reg(dev, &mmsys->cmdq_base, 0);
> + if (ret)
> + dev_dbg(dev, "No mediatek,gce-client-reg!\n");
> +#endif
> +
> platform_set_drvdata(pdev, mmsys);
>
> clks = platform_device_register_data(&pdev->dev, mmsys->data-
> >clk_driver,
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h
> b/include/linux/soc/mediatek/mtk-mmsys.h
> index fe620929b0f9..7a73305390ba 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -6,6 +6,10 @@
> #ifndef __MTK_MMSYS_H
> #define __MTK_MMSYS_H
>
> +#include <linux/mailbox_controller.h>
> +#include <linux/mailbox/mtk-cmdq-mailbox.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
> +
> enum mtk_ddp_comp_id;
> struct device;
>
> @@ -73,13 +77,16 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> enum mtk_ddp_comp_id cur,
> enum mtk_ddp_comp_id next);
>
> -void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> width, int height);
> +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int
> width,
> + int height, struct cmdq_pkt
> *cmdq_pkt);
>
> -void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int
> be_height);
> +void mtk_mmsys_hdr_confing(struct device *dev, int be_width, int
> be_height,
> + struct cmdq_pkt *cmdq_pkt);
>
> void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool
> alpha_sel, u16 alpha,
> - u8 mode, u32 biwidth);
> + u8 mode, u32 biwidth, struct cmdq_pkt
> *cmdq_pkt);
>
> -void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> bool channel_swap);
> +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx,
> bool channel_swap,
> + struct cmdq_pkt *cmdq_pkt);
>
> #endif /* __MTK_MMSYS_H */