From: Nancy.Lin <nancy.lin@mediatek.com>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
CK Hu <ck.hu@mediatek.com>
Cc: Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tom Rix <trix@redhat.com>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
"Jason-JH . Lin" <jason-jh.lin@mediatek.com>,
"Nancy . Lin" <nancy.lin@mediatek.com>,
Nathan Lu <nathan.lu@mediatek.com>,
Rex-BC Chen <rex-bc.chen@mediatek.com>,
Xinlei Lee <xinlei.lee@mediatek.com>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>, <llvm@lists.linux.dev>,
<singo.chang@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>
Subject: [PATCH v30 02/11] dt-bindings: reset: mt8195: add vdosys1 reset control bit
Date: Fri, 13 Jan 2023 18:44:25 +0800 [thread overview]
Message-ID: <20230113104434.28023-3-nancy.lin@mediatek.com> (raw)
In-Reply-To: <20230113104434.28023-1-nancy.lin@mediatek.com>
Add vdosys1 reset control bit for MT8195 platform.
Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
include/dt-bindings/reset/mt8195-resets.h | 45 +++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/include/dt-bindings/reset/mt8195-resets.h b/include/dt-bindings/reset/mt8195-resets.h
index 24ab3631dcea..e61660438d61 100644
--- a/include/dt-bindings/reset/mt8195-resets.h
+++ b/include/dt-bindings/reset/mt8195-resets.h
@@ -35,4 +35,49 @@
#define MT8195_INFRA_RST2_PCIE_P1_SWRST 4
#define MT8195_INFRA_RST2_USBSIF_P1_SWRST 5
+/* VDOSYS1 */
+#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB2 0
+#define MT8195_VDOSYS1_SW0_RST_B_SMI_LARB3 1
+#define MT8195_VDOSYS1_SW0_RST_B_GALS 2
+#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG0 3
+#define MT8195_VDOSYS1_SW0_RST_B_FAKE_ENG1 4
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA0 5
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA1 6
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA2 7
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA3 8
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE0 9
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE1 10
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE2 11
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE3 12
+#define MT8195_VDOSYS1_SW0_RST_B_VPP_MERGE4 13
+#define MT8195_VDOSYS1_SW0_RST_B_VPP2_TO_VDO1_DL_ASYNC 14
+#define MT8195_VDOSYS1_SW0_RST_B_VPP3_TO_VDO1_DL_ASYNC 15
+#define MT8195_VDOSYS1_SW0_RST_B_DISP_MUTEX 16
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA4 17
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA5 18
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA6 19
+#define MT8195_VDOSYS1_SW0_RST_B_MDP_RDMA7 20
+#define MT8195_VDOSYS1_SW0_RST_B_DP_INTF0 21
+#define MT8195_VDOSYS1_SW0_RST_B_DPI0 22
+#define MT8195_VDOSYS1_SW0_RST_B_DPI1 23
+#define MT8195_VDOSYS1_SW0_RST_B_DISP_MONITOR 24
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE0_DL_ASYNC 25
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE1_DL_ASYNC 26
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE2_DL_ASYNC 27
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE3_DL_ASYNC 28
+#define MT8195_VDOSYS1_SW0_RST_B_MERGE4_DL_ASYNC 29
+#define MT8195_VDOSYS1_SW0_RST_B_VDO0_DSC_TO_VDO1_DL_ASYNC 30
+#define MT8195_VDOSYS1_SW0_RST_B_VDO0_MERGE_TO_VDO1_DL_ASYNC 31
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0 32
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0 33
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE 34
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1 48
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1 49
+#define MT8195_VDOSYS1_SW1_RST_B_DISP_MIXER 50
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC 51
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC 52
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC 53
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC 54
+#define MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC 55
+
#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT8195 */
--
2.18.0
next prev parent reply other threads:[~2023-01-13 10:44 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-13 10:44 [PATCH v30 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195 Nancy.Lin
2023-01-13 11:19 ` Krzysztof Kozlowski
2023-01-13 10:44 ` Nancy.Lin [this message]
2023-01-13 10:44 ` [PATCH v30 03/11] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 07/11] soc: mediatek: add cmdq support of " Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 08/11] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 09/11] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 10/11] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
2023-01-13 10:44 ` [PATCH v30 11/11] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
2023-01-20 11:10 ` [PATCH v30 00/11] Add MediaTek SoC(vdosys1) support for mt8195 AngeloGioacchino Del Regno
2023-01-25 15:05 ` Matthias Brugger
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