From: Sunil V L <sunilvl@ventanamicro.com>
To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-crypto@vger.kernel.org,
platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev
Cc: Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
"Rafael J . Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Weili Qian <qianweili@huawei.com>,
Zhou Wang <wangzhou1@hisilicon.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
"David S . Miller" <davem@davemloft.net>,
Marc Zyngier <maz@kernel.org>,
Maximilian Luz <luzmaximilian@gmail.com>,
Hans de Goede <hdegoede@redhat.com>,
Mark Gross <markgross@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tom Rix <trix@redhat.com>, Sunil V L <sunilvl@ventanamicro.com>
Subject: [PATCH V5 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang
Date: Mon, 8 May 2023 17:22:19 +0530 [thread overview]
Message-ID: <20230508115237.216337-4-sunilvl@ventanamicro.com> (raw)
In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com>
With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in
allmodconfig build. However, build fails with clang and below
error is seen.
drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm
"+Q" (*((char __iomem *)fun_base))
^
This is expected error with clang due to the way it is designed.
To fix this issue, move arm64 assembly code under #if.
Link: https://github.com/ClangBuiltLinux/linux/issues/999
Signed-off-by: Nathan Chancellor <nathan@kernel.org>
[sunilvl@ventanamicro.com: Moved tmp0 and tmp1 into the #if]
Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
---
drivers/crypto/hisilicon/qm.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c
index ad0c042b5e66..2eaeaac2e246 100644
--- a/drivers/crypto/hisilicon/qm.c
+++ b/drivers/crypto/hisilicon/qm.c
@@ -610,13 +610,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready);
static void qm_mb_write(struct hisi_qm *qm, const void *src)
{
void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
- unsigned long tmp0 = 0, tmp1 = 0;
- if (!IS_ENABLED(CONFIG_ARM64)) {
- memcpy_toio(fun_base, src, 16);
- dma_wmb();
- return;
- }
+#if IS_ENABLED(CONFIG_ARM64)
+ unsigned long tmp0 = 0, tmp1 = 0;
asm volatile("ldp %0, %1, %3\n"
"stp %0, %1, %2\n"
@@ -626,6 +622,11 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src)
"+Q" (*((char __iomem *)fun_base))
: "Q" (*((char *)src))
: "memory");
+#else
+ memcpy_toio(fun_base, src, 16);
+ dma_wmb();
+#endif
+
}
static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox)
--
2.34.1
next prev parent reply other threads:[~2023-05-08 11:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-08 11:52 [PATCH V5 00/21] Add basic ACPI support for RISC-V Sunil V L
2023-05-08 11:52 ` [PATCH V5 01/21] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-05-08 11:52 ` [PATCH V5 02/21] platform/surface: Disable for RISC-V Sunil V L
2023-05-08 11:52 ` Sunil V L [this message]
2023-05-09 2:17 ` [PATCH V5 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Herbert Xu
2023-05-10 5:47 ` Sunil V L
2023-05-08 11:52 ` [PATCH V5 04/21] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-05-08 11:52 ` [PATCH V5 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-05-08 11:52 ` [PATCH V5 06/21] RISC-V: Add support to build the ACPI core Sunil V L
2023-05-08 11:52 ` [PATCH V5 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-05-08 11:52 ` [PATCH V5 08/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-05-09 17:50 ` Conor Dooley
2023-05-10 3:46 ` Sunil V L
2023-05-08 11:52 ` [PATCH V5 09/21] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-05-08 11:52 ` [PATCH V5 10/21] RISC-V: smpboot: Create wrapper setup_smp() Sunil V L
2023-05-08 11:52 ` [PATCH V5 11/21] RISC-V: smpboot: Add ACPI support in setup_smp() Sunil V L
2023-05-08 11:52 ` [PATCH V5 12/21] RISC-V: only iterate over possible CPUs in ISA string parser Sunil V L
2023-05-08 11:52 ` [PATCH V5 13/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-05-08 11:52 ` [PATCH V5 14/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-05-08 11:52 ` [PATCH V5 15/21] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-05-08 11:52 ` [PATCH V5 16/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-05-08 11:52 ` [PATCH V5 17/21] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-05-08 11:52 ` [PATCH V5 18/21] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-05-08 11:52 ` [PATCH V5 19/21] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-05-08 11:52 ` [PATCH V5 20/21] RISC-V: Enable ACPI in defconfig Sunil V L
2023-05-08 11:52 ` [PATCH V5 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
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