Re: [PATCH v4] mips: add <asm-generic/io.h> including

kernel test robot
2023-05-26T09:46:29Z

Hi Jiaxun,

kernel test robot noticed the following build warnings:

[auto build test WARNING on soc/for-next]
[also build test WARNING on linus/master v6.4-rc3 next-20230525]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url: https://github.com/intel-lab-lkp/linux/commits/Jiaxun-Yang/mips-add-asm-generic-io-h-including/20230520-035318
base: https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git for-next
patch link: https://lore.kernel.org/r/20230519195135.79600-1-jiaxun.yang%40flygoat.com
patch subject: [PATCH v4] mips: add <asm-generic/io.h> including
config: mips-randconfig-r015-20230525 (https://download.01.org/0day-ci/archive/20230526/202305261736.cBisGOAz-lkp@intel.com/config)
compiler: clang version 17.0.0 (https://github.com/llvm/llvm-project 4faf3aaf28226a4e950c103a14f6fc1d1fdabb1b)
reproduce (this is a W=1 build):
mkdir -p ~/bin
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install mips cross compiling tool for clang build
# apt-get install binutils-mips-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/4f10a6993ab8060829908b87cdeea41f7eae38e7
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Jiaxun-Yang/mips-add-asm-generic-io-h-including/20230520-035318
git checkout 4f10a6993ab8060829908b87cdeea41f7eae38e7
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang ~/bin/make.cross W=1 O=build_dir ARCH=mips olddefconfig
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang ~/bin/make.cross W=1 O=build_dir ARCH=mips SHELL=/bin/bash drivers/mmc/

If you fix the issue, kindly add following tag where applicable
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202305261736.cBisGOAz-lkp@intel.com/

All warnings (new ones prefixed by >>):

In file included from drivers/mmc/host/dw_mmc.c:41:
>> drivers/mmc/host/dw_mmc.h:506:9: warning: '__raw_writeq' macro redefined [-Wmacro-redefined]
#define __raw_writeq(__value, __reg) \
^
arch/mips/include/asm/io.h:566:9: note: previous definition is here
#define __raw_writeq __raw_writeq
^
In file included from drivers/mmc/host/dw_mmc.c:41:
>> drivers/mmc/host/dw_mmc.h:508:9: warning: '__raw_readq' macro redefined [-Wmacro-redefined]
#define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
^
arch/mips/include/asm/io.h:562:9: note: previous definition is here
#define __raw_readq __raw_readq
^
2 warnings generated.

vim +/__raw_writeq +506 drivers/mmc/host/dw_mmc.h

76184ac17edf3c Ben Dooks 2015-03-25 473
f95f3850f7a9e1 Will Newton 2011-01-02 474 /* Register access macros */
f95f3850f7a9e1 Will Newton 2011-01-02 475 #define mci_readl(dev, reg) \
a2f17680f42878 Ben Dooks 2015-03-25 476 readl_relaxed((dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 477 #define mci_writel(dev, reg, value) \
a2f17680f42878 Ben Dooks 2015-03-25 478 writel_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 479
f95f3850f7a9e1 Will Newton 2011-01-02 480 /* 16-bit FIFO access macros */
f95f3850f7a9e1 Will Newton 2011-01-02 481 #define mci_readw(dev, reg) \
a2f17680f42878 Ben Dooks 2015-03-25 482 readw_relaxed((dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 483 #define mci_writew(dev, reg, value) \
a2f17680f42878 Ben Dooks 2015-03-25 484 writew_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 485
f95f3850f7a9e1 Will Newton 2011-01-02 486 /* 64-bit FIFO access macros */
f95f3850f7a9e1 Will Newton 2011-01-02 487 #ifdef readq
f95f3850f7a9e1 Will Newton 2011-01-02 488 #define mci_readq(dev, reg) \
a2f17680f42878 Ben Dooks 2015-03-25 489 readq_relaxed((dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 490 #define mci_writeq(dev, reg, value) \
a2f17680f42878 Ben Dooks 2015-03-25 491 writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
f95f3850f7a9e1 Will Newton 2011-01-02 492 #else
f95f3850f7a9e1 Will Newton 2011-01-02 493 /*
f95f3850f7a9e1 Will Newton 2011-01-02 494 * Dummy readq implementation for architectures that don't define it.
f95f3850f7a9e1 Will Newton 2011-01-02 495 *
f95f3850f7a9e1 Will Newton 2011-01-02 496 * We would assume that none of these architectures would configure
f95f3850f7a9e1 Will Newton 2011-01-02 497 * the IP block with a 64bit FIFO width, so this code will never be
f95f3850f7a9e1 Will Newton 2011-01-02 498 * executed on those machines. Defining these macros here keeps the
f95f3850f7a9e1 Will Newton 2011-01-02 499 * rest of the code free from ifdefs.
f95f3850f7a9e1 Will Newton 2011-01-02 500 */
f95f3850f7a9e1 Will Newton 2011-01-02 501 #define mci_readq(dev, reg) \
892b1e312b1791 James Hogan 2011-06-24 502 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
f95f3850f7a9e1 Will Newton 2011-01-02 503 #define mci_writeq(dev, reg, value) \
892b1e312b1791 James Hogan 2011-06-24 504 (*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
76184ac17edf3c Ben Dooks 2015-03-25 505
76184ac17edf3c Ben Dooks 2015-03-25 @506 #define __raw_writeq(__value, __reg) \
76184ac17edf3c Ben Dooks 2015-03-25 507 (*(volatile u64 __force *)(__reg) = (__value))
76184ac17edf3c Ben Dooks 2015-03-25 @508 #define __raw_readq(__reg) (*(volatile u64 __force *)(__reg))
f95f3850f7a9e1 Will Newton 2011-01-02 509 #endif
f95f3850f7a9e1 Will Newton 2011-01-02 510

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