From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-yb1-f202.google.com (mail-yb1-f202.google.com [209.85.219.202]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 23909156FD for ; Tue, 15 Aug 2023 20:34:47 +0000 (UTC) Received: by mail-yb1-f202.google.com with SMTP id 3f1490d57ef6-c6dd0e46a52so6430049276.2 for ; Tue, 15 Aug 2023 13:34:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20221208; t=1692131687; x=1692736487; h=cc:to:from:subject:message-id:mime-version:date:from:to:cc:subject :date:message-id:reply-to; bh=Vu3YlGSzqXzwwgWi/q2n2LUyYRgXMju9WJu57GL76pk=; b=20AONJpHkDmgRGgvrCxY0YZ8+qqnTitvPIFm7bIiayyUYFEQqFxqWYX8evjU2xIyUw kjDuIsOilMdRoalLKR77olLsbFjaAed3/7DHNZLY8sSj7RzpE3XHC1oIJpS5fO3DdjZs eGslVcDajvPI8Rde/nLOFVgo9XIrAhuny8kJs3Bti6SoSKx0omgX3hzEuQX36GvVbFff 2deWtQZiWKLYyFOy6UiM2NxkHW3lvNnozvk+9w3XjLcmLksHncKXXh4v5EzHm4vLOyJc HBhwBE8ay/jX0hjbzZVvnLB1TnzbvlCw64myqkQrR1wHFoJU0qpNclkIh421HKlMKCTj foPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1692131687; x=1692736487; h=cc:to:from:subject:message-id:mime-version:date:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=Vu3YlGSzqXzwwgWi/q2n2LUyYRgXMju9WJu57GL76pk=; b=R3uRN05Kb4MQ7ijiBPG7Z4K2PQDbCCuUW2mGacT3829esLzxEQineYnWiUs600HFl0 0gx4WyX0TArf7IxY0+e1DO9NoqSqP4mEJLJRsUu9vwDUU3T3GKZVZ82J5S6ajO5UgjLm 4UvwcmHQ42ajicLvh67H//Jo2uiUbmHp48E9TWKymkj0Nb/6+Dt8dojpkWjP+PQUDJru FByD82oIHhqPrEYsY64KDedpki6wTdaRMcvA5ZBLZa2AcUsvYiX+LCQJkxwDcbwrfPWi 83pX1xvZyw6uP2lW1ToSmNbL9AvTX2x1jav/YbjTjryg8bl6bJQNKIz1aOHpan0Gu5zL X26Q== X-Gm-Message-State: AOJu0YxwB99srYCSznnF2HaiPuqSH3BEC7FfEm8Z1VUGHOmgJWk63IK7 iz7P90RzZBi26eJgRh9hCDalaEq+7tPDWa5ZmbE= X-Google-Smtp-Source: AGHT+IEEEB9RkxNGC3nmjrLzfqaEjo04hgJYb9l9GY8BmhXIPcxgYphL1eVtvENoj53ebcdCaRYUhQD32EVakIpj8/M= X-Received: from samitolvanen.c.googlers.com ([fda3:e722:ac3:cc00:7f:e700:c0a8:4f92]) (user=samitolvanen job=sendgmr) by 2002:a05:6902:565:b0:d18:73fc:40af with SMTP id a5-20020a056902056500b00d1873fc40afmr177279ybt.5.1692131686943; Tue, 15 Aug 2023 13:34:46 -0700 (PDT) Date: Tue, 15 Aug 2023 20:34:43 +0000 Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 X-Developer-Key: i=samitolvanen@google.com; a=openpgp; fpr=35CCFB63B283D6D3AEB783944CB5F6848BBC56EE X-Developer-Signature: v=1; a=openpgp-sha256; l=3258; i=samitolvanen@google.com; h=from:subject; bh=27ja0uIMORSaGulxExOcQfSpvjxiVAnXn8qbTbuF2b0=; b=owEB7QES/pANAwAKAUy19oSLvFbuAcsmYgBk2+Fi/AuN72l+gcV8yqSSBdN3XwK5ap26p2ccW t4HA4fLgSGJAbMEAAEKAB0WIQQ1zPtjsoPW0663g5RMtfaEi7xW7gUCZNvhYgAKCRBMtfaEi7xW 7r6jC/sH51moOTq9GAgfZW4dtbVJIZrfYUSzK4jLvJmepsTXYq94/9JqoarL8IMhVnGC323YKZr E8A8U0U0WxapNQYW0Z0Q6wamv9b2xwueVG8zXctXXNPZsr8+jSzettmfIZjoB2uhItHSpHotq70 iaOJ0gj83hEfx5sej+dGuPOo1tlpXxS1TYm7BVRz+7mAg8U1+4tFwVTi/22JzmAmvNwhc6YeEgX uE+/tftT10bAT8AEYZYiX3Q+MMBvT6cQtj5ybfDWHwHkd4hhWXNlIw9k+gaFc1L2/yoPx53SwS+ ISUe54u+RjDb3YNfPy4JpwNdXcFQl3F3Aq7C0d2jI92BeRVINzB9MB1EtqPf01LvLnje/IhJJci ckDpO8njNWQ7J30a147p197hlPwd3LLqXp1YNxeBugtDRxtrbe9dAE1gUQJ3MbzGyhbJAmM5r3S /Li1U6ZyGOsoSDe2NClMgfhbi1GavCoEXC7ieC0iD4U6Oyxr4auvV2u+bGy0MWWimJbx8= X-Mailer: git-send-email 2.41.0.694.ge786442a9b-goog Message-ID: <20230815203442.1608773-8-samitolvanen@google.com> Subject: [PATCH v2 0/6] riscv: SCS support From: Sami Tolvanen To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Kees Cook Cc: Guo Ren , Deepak Gupta , Nathan Chancellor , Nick Desaulniers , Fangrui Song , linux-riscv@lists.infradead.org, llvm@lists.linux.dev, linux-kernel@vger.kernel.org, Sami Tolvanen Content-Type: text/plain; charset="UTF-8" Hi folks, This series adds Shadow Call Stack (SCS) support for RISC-V. SCS uses compiler instrumentation to store return addresses in a separate shadow stack to protect them against accidental or malicious overwrites. More information about SCS can be found here: https://clang.llvm.org/docs/ShadowCallStack.html Patch 1 is from Deepak, and it simplifies VMAP_STACK overflow handling by adding support for accessing per-CPU variables directly in assembly. The patch is included in this series to make IRQ stack switching cleaner with SCS, and I've simply rebased it. Patch 2 uses this functionality to clean up the stack switching by moving duplicate code into a single function. On RISC-V, the compiler uses the gp register for storing the current shadow call stack pointer, which is incompatible with global pointer relaxation. Patch 3 moves global pointer loading into a macro that can be easily disabled with SCS. Patch 4 implements SCS register loading and switching, and allows the feature to be enabled, and patch 5 adds separate per-CPU IRQ shadow call stacks when CONFIG_IRQ_STACKS is enabled. Patch 6 fixes the backward- edge CFI test in lkdtm for RISC-V. Note that this series requires Clang 17. Earlier Clang versions support SCS on RISC-V, but use the x18 register instead of gp, which isn't ideal. gcc has SCS support for arm64, but I'm not aware of plans to support RISC-V. Once the Zicfiss extension is ratified, it's probably preferable to use hardware-backed shadow stacks instead of SCS on hardware that supports the extension, and we may want to consider implementing CONFIG_DYNAMIC_SCS to patch between the implementation at runtime (similarly to the arm64 implementation, which switches to SCS when hardware PAC support isn't available). Sami --- Changes in v2: - Fixed asm_per_cpu with !CONFIG_SMP. - Added patch 6 to fix the CFI_BACKWARD lkdtm test. - Rebased on top of -rc6. --- Deepak Gupta (1): riscv: VMAP_STACK overflow detection thread-safe Sami Tolvanen (5): riscv: Deduplicate IRQ stack switching riscv: Move global pointer loading to a macro riscv: Implement Shadow Call Stack riscv: Use separate IRQ shadow call stacks lkdtm: Fix CFI_BACKWARD on RISC-V arch/riscv/Kconfig | 6 ++ arch/riscv/Makefile | 4 + arch/riscv/include/asm/asm.h | 41 +++++++++ arch/riscv/include/asm/irq_stack.h | 3 + arch/riscv/include/asm/scs.h | 54 ++++++++++++ arch/riscv/include/asm/thread_info.h | 16 +++- arch/riscv/kernel/asm-offsets.c | 4 + arch/riscv/kernel/entry.S | 126 +++++++++++++-------------- arch/riscv/kernel/head.S | 19 ++-- arch/riscv/kernel/irq.c | 53 ++++++----- arch/riscv/kernel/suspend_entry.S | 5 +- arch/riscv/kernel/traps.c | 65 ++------------ arch/riscv/kernel/vdso/Makefile | 2 +- arch/riscv/purgatory/Makefile | 4 + drivers/misc/lkdtm/cfi.c | 13 ++- 15 files changed, 245 insertions(+), 170 deletions(-) create mode 100644 arch/riscv/include/asm/scs.h base-commit: 2ccdd1b13c591d306f0401d98dedc4bdcd02b421 -- 2.41.0.694.ge786442a9b-goog