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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-390e4848252sm21356612f8f.69.2025.03.05.06.26.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 06:26:54 -0800 (PST) Date: Wed, 5 Mar 2025 14:26:53 +0000 From: David Laight To: Eric Biggers Cc: linux-kernel@vger.kernel.org, Bill Wendling , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H . Peter Anvin" , Ard Biesheuvel , Nathan Chancellor , Nick Desaulniers , Justin Stitt , linux-crypto@vger.kernel.org, llvm@lists.linux.dev Subject: Re: [PATCH] x86/crc32: optimize tail handling for crc32c short inputs Message-ID: <20250305142653.751d9840@pumpkin> In-Reply-To: <20250304213216.108925-1-ebiggers@kernel.org> References: <20250304213216.108925-1-ebiggers@kernel.org> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Tue, 4 Mar 2025 13:32:16 -0800 Eric Biggers wrote: > From: Eric Biggers > > For handling the 0 <= len < sizeof(unsigned long) bytes left at the end, > do a 4-2-1 step-down instead of a byte-at-a-time loop. This allows > taking advantage of wider CRC instructions. Note that crc32c-3way.S > already uses this same optimization too. An alternative is to add extra zero bytes at the start of the buffer. They don't affect the crc and just need the first 8 bytes shifted left. I think any non-zero 'crc-in' just needs to be xor'ed over the first 4 actual data bytes. (It's over 40 years since I did the maths of CRC.) You won't notice the misaligned accesses all down the buffer. When I was testing different ipcsum code misaligned buffers cost less than 1 clock per cache line. I think that was even true for the versions that managed 12 bytes per clock (including the one Linus committed). David