Re: [RFC PATCH] cxl/region: Translate DPA->HPA in unaligned MOD3 regions

[kernel test robot <lkp@intel.com>]

Hi,

[This is a private test report for your RFC patch.]
kernel test robot noticed the following build warnings:

[auto build test WARNING on 26600bf10173beda5358d194ec425a1cfafa2fe2]

url:    https://github.com/intel-lab-lkp/linux/commits/alison-schofield-intel-com/cxl-region-Translate-DPA-HPA-in-unaligned-MOD3-regions/20250307-034424
base:   26600bf10173beda5358d194ec425a1cfafa2fe2
patch link:    https://lore.kernel.org/r/20250306194328.2600429-1-alison.schofield%40intel.com
patch subject: [RFC PATCH] cxl/region: Translate DPA->HPA in unaligned MOD3 regions
config: arm-randconfig-001-20250307 (https://download.01.org/0day-ci/archive/20250307/202503070931.7aNcyFaJ-lkp@intel.com/config)
compiler: clang version 21.0.0git (https://github.com/llvm/llvm-project 14170b16028c087ca154878f5ed93d3089a965c6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250307/202503070931.7aNcyFaJ-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202503070931.7aNcyFaJ-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/cxl/core/region.c:2976:3: warning: format specifies type 'unsigned long long' but the argument has type 'resource_size_t' (aka 'unsigned int') [-Wformat]
    2975 |         dev_dbg(&cxld->dev, "fail dpa:%#llx start:%#llx pos:%d\n", dpa,
         |                                                   ~~~~~
         |                                                   %#x
    2976 |                 p->res->start, pos);
         |                 ^~~~~~~~~~~~~
   include/linux/dev_printk.h:165:39: note: expanded from macro 'dev_dbg'
     165 |         dynamic_dev_dbg(dev, dev_fmt(fmt), ##__VA_ARGS__)
         |                                      ~~~     ^~~~~~~~~~~
   include/linux/dynamic_debug.h:274:19: note: expanded from macro 'dynamic_dev_dbg'
     274 |                            dev, fmt, ##__VA_ARGS__)
         |                                 ~~~    ^~~~~~~~~~~
   include/linux/dynamic_debug.h:250:59: note: expanded from macro '_dynamic_func_call'
     250 |         _dynamic_func_call_cls(_DPRINTK_CLASS_DFLT, fmt, func, ##__VA_ARGS__)
         |                                                                  ^~~~~~~~~~~
   include/linux/dynamic_debug.h:248:65: note: expanded from macro '_dynamic_func_call_cls'
     248 |         __dynamic_func_call_cls(__UNIQUE_ID(ddebug), cls, fmt, func, ##__VA_ARGS__)
         |                                                                        ^~~~~~~~~~~
   include/linux/dynamic_debug.h:224:15: note: expanded from macro '__dynamic_func_call_cls'
     224 |                 func(&id, ##__VA_ARGS__);                       \
         |                             ^~~~~~~~~~~
   1 warning generated.


vim +2976 drivers/cxl/core/region.c

  2932	
  2933	/*
  2934	 * unaligned_dpa_to_hpa() translates a DPA to HPA when the region resource
  2935	 * start address is not a multiple of the Host Bridge interleave ways.
  2936	 *
  2937	 * Unaligned address translation is only supported for regions built upon
  2938	 * 3-way HB interleaves, 1+1+1 2+2+2 4+4+4+4, and will fail on any other
  2939	 * unaligned regions. ie. if a 4-way region appears with an unaligned start
  2940	 * address it fails at the decode_pos().
  2941	 */
  2942	static u64 unaligned_dpa_to_hpa(struct cxl_decoder *cxld,
  2943					struct cxl_region_params *p, int pos, u64 dpa)
  2944	{
  2945		int ways_port = p->interleave_ways / cxld->interleave_ways;
  2946		int gran_port = p->interleave_granularity;
  2947		int gran_hb = cxld->interleave_granularity;
  2948		int ways_hb = cxld->interleave_ways;
  2949		u64 hpa, hpa_port = 0;
  2950		int pos_port, pos_hb;
  2951	
  2952		/* Decode an endpoint 'pos' into port and host-bridge components */
  2953		if (decode_pos(p->interleave_ways, pos, &pos_port, &pos_hb)) {
  2954			dev_dbg(&cxld->dev, "not supported for region ways:%d\n",
  2955				p->interleave_ways);
  2956			return ULLONG_MAX;
  2957		}
  2958		/* Restore the port parent address if needed */
  2959		/* This could also be 'if (region ways > 3)' for this limited soln */
  2960		if (gran_hb != gran_port)
  2961			hpa_port = restore_parent(dpa, pos_port, gran_port, ways_port);
  2962	
  2963		/*
  2964		 * Complete the HPA reconstruction by restoring the address as if
  2965		 * each HB position is a candidate. Test against expected pos_hb
  2966		 * to confirm match.
  2967		 */
  2968		for (int index = 0; index < ways_hb; index++) {
  2969			hpa = restore_parent(hpa_port, index, gran_hb, ways_hb);
  2970			hpa += p->res->start;
  2971			if ((hpa / gran_hb) % ways_hb == pos_hb)
  2972				return hpa;
  2973		}
  2974	
  2975		dev_dbg(&cxld->dev, "fail dpa:%#llx start:%#llx pos:%d\n", dpa,
> 2976			p->res->start, pos);
  2977		dev_dbg(&cxld->dev, "     port-w/g/p:%d/%d/%d hb-w/g/p:%d/%d/%d\n",
  2978			ways_port, gran_port, pos_port, ways_hb, gran_hb, pos_hb);
  2979	
  2980		return ULLONG_MAX;
  2981	}
  2982	

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