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charset=us-ascii Content-Disposition: inline tree: https://git.kernel.org/pub/scm/linux/kernel/git/jpoimboe/linux.git objtool-werror head: aecd65419533fc7a9eb88c055189d4ec4c9fbdca commit: 38fca6d9fa6497b95c4b53427d3e83908b807cf3 [9/21] pwm: mediatek: Prevent divide-by-zero in pwm_mediatek_config() config: i386-buildonly-randconfig-004-20250323 (https://download.01.org/0day-ci/archive/20250323/202503231837.DYHg04BB-lkp@intel.com/config) compiler: clang version 20.1.1 (https://github.com/llvm/llvm-project 424c2d9b7e4de40d0804dd374721e6411c27d1d1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250323/202503231837.DYHg04BB-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202503231837.DYHg04BB-lkp@intel.com/ All errors (new ones prefixed by >>): >> drivers/pwm/pwm-mediatek.c:142:34: error: incompatible integer to pointer conversion passing 'unsigned long' to parameter of type 'struct clk *' [-Wint-conversion] 142 | do_div(resolution, clk_get_rate(clk_rate)); | ^~~~~~~~ arch/x86/include/asm/div64.h:25:12: note: expanded from macro 'do_div' 25 | __base = (base); \ | ^~~~ include/linux/clk.h:751:40: note: passing argument to parameter 'clk' here 751 | unsigned long clk_get_rate(struct clk *clk); | ^ 1 error generated. vim +142 drivers/pwm/pwm-mediatek.c 117 118 static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, 119 int duty_ns, int period_ns) 120 { 121 struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); 122 u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, 123 reg_thres = PWMTHRES; 124 unsigned long clk_rate; 125 u64 resolution; 126 int ret; 127 128 ret = pwm_mediatek_clk_enable(chip, pwm); 129 if (ret < 0) 130 return ret; 131 132 clk_rate = clk_get_rate(pc->clk_pwms[pwm->hwpwm]); 133 if (!clk_rate) 134 return -EINVAL; 135 136 /* Make sure we use the bus clock and not the 26MHz clock */ 137 if (pc->soc->has_ck_26m_sel) 138 writel(0, pc->regs + PWM_CK_26M_SEL); 139 140 /* Using resolution in picosecond gets accuracy higher */ 141 resolution = (u64)NSEC_PER_SEC * 1000; > 142 do_div(resolution, clk_get_rate(clk_rate)); 143 144 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); 145 while (cnt_period > 8191) { 146 resolution *= 2; 147 clkdiv++; 148 cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, 149 resolution); 150 } 151 152 if (clkdiv > PWM_CLK_DIV_MAX) { 153 pwm_mediatek_clk_disable(chip, pwm); 154 dev_err(pwmchip_parent(chip), "period of %d ns not supported\n", period_ns); 155 return -EINVAL; 156 } 157 158 if (pc->soc->pwm45_fixup && pwm->hwpwm > 2) { 159 /* 160 * PWM[4,5] has distinct offset for PWMDWIDTH and PWMTHRES 161 * from the other PWMs on MT7623. 162 */ 163 reg_width = PWM45DWIDTH_FIXUP; 164 reg_thres = PWM45THRES_FIXUP; 165 } 166 167 cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); 168 pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); 169 pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); 170 pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); 171 172 pwm_mediatek_clk_disable(chip, pwm); 173 174 return 0; 175 } 176 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki