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charset=us-ascii Content-Disposition: inline Hi Uros, FYI, the error/warning was bisected to this commit, please ignore it if it's irrelevant. tree: https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git x86/mm head: 6c921984e75c78e1c509d99b8cde04f1eadd46fb commit: cd3b85b27542968198e3d588a2bc0591930ee2ee [7/9] x86/idle: Use MONITOR and MWAIT mnemonics in config: x86_64-buildonly-randconfig-003-20250403 (https://download.01.org/0day-ci/archive/20250403/202504030802.2lEVBSpN-lkp@intel.com/config) compiler: clang version 20.1.1 (https://github.com/llvm/llvm-project 424c2d9b7e4de40d0804dd374721e6411c27d1d1) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20250403/202504030802.2lEVBSpN-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202504030802.2lEVBSpN-lkp@intel.com/ All errors (new ones prefixed by >>): In file included from arch/x86/kernel/process.c:36: >> arch/x86/include/asm/mwait.h:30:15: error: invalid operand for instruction 30 | asm volatile("monitor %0, %1, %2" :: "a" (eax), "c" (ecx), "d" (edx)); | ^ :1:16: note: instantiated into assembly here 1 | monitor %rax, %ecx, %edx | ^~~~~ In file included from arch/x86/kernel/process.c:36: >> arch/x86/include/asm/mwait.h:95:15: error: instruction requires: Not 64-bit mode 95 | asm volatile("sti; mwait %0, %1" :: "a" (eax), "c" (ecx)); | ^ :1:7: note: instantiated into assembly here 1 | sti; mwait %eax, %ecx | ^ 2 errors generated. vim +30 arch/x86/include/asm/mwait.h 27 28 static __always_inline void __monitor(const void *eax, u32 ecx, u32 edx) 29 { > 30 asm volatile("monitor %0, %1, %2" :: "a" (eax), "c" (ecx), "d" (edx)); 31 } 32 33 static __always_inline void __monitorx(const void *eax, u32 ecx, u32 edx) 34 { 35 /* "monitorx %eax, %ecx, %edx;" */ 36 asm volatile(".byte 0x0f, 0x01, 0xfa;" 37 :: "a" (eax), "c" (ecx), "d"(edx)); 38 } 39 40 static __always_inline void __mwait(u32 eax, u32 ecx) 41 { 42 mds_idle_clear_cpu_buffers(); 43 44 asm volatile("mwait %0, %1" :: "a" (eax), "c" (ecx)); 45 } 46 47 /* 48 * MWAITX allows for a timer expiration to get the core out a wait state in 49 * addition to the default MWAIT exit condition of a store appearing at a 50 * monitored virtual address. 51 * 52 * Registers: 53 * 54 * MWAITX ECX[1]: enable timer if set 55 * MWAITX EBX[31:0]: max wait time expressed in SW P0 clocks. The software P0 56 * frequency is the same as the TSC frequency. 57 * 58 * Below is a comparison between MWAIT and MWAITX on AMD processors: 59 * 60 * MWAIT MWAITX 61 * opcode 0f 01 c9 | 0f 01 fb 62 * ECX[0] value of RFLAGS.IF seen by instruction 63 * ECX[1] unused/#GP if set | enable timer if set 64 * ECX[31:2] unused/#GP if set 65 * EAX unused (reserve for hint) 66 * EBX[31:0] unused | max wait time (P0 clocks) 67 * 68 * MONITOR MONITORX 69 * opcode 0f 01 c8 | 0f 01 fa 70 * EAX (logical) address to monitor 71 * ECX #GP if not zero 72 */ 73 static __always_inline void __mwaitx(u32 eax, u32 ebx, u32 ecx) 74 { 75 /* No MDS buffer clear as this is AMD/HYGON only */ 76 77 /* "mwaitx %eax, %ebx, %ecx;" */ 78 asm volatile(".byte 0x0f, 0x01, 0xfb;" 79 :: "a" (eax), "b" (ebx), "c" (ecx)); 80 } 81 82 /* 83 * Re-enable interrupts right upon calling mwait in such a way that 84 * no interrupt can fire _before_ the execution of mwait, ie: no 85 * instruction must be placed between "sti" and "mwait". 86 * 87 * This is necessary because if an interrupt queues a timer before 88 * executing mwait, it would otherwise go unnoticed and the next tick 89 * would not be reprogrammed accordingly before mwait ever wakes up. 90 */ 91 static __always_inline void __sti_mwait(u32 eax, u32 ecx) 92 { 93 mds_idle_clear_cpu_buffers(); 94 > 95 asm volatile("sti; mwait %0, %1" :: "a" (eax), "c" (ecx)); 96 } 97 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki