[arnd-playground:to-build 6/9] arch/arm64/include/asm/cache.h:69:9: error: call to undeclared function '_test_bit'; ISO C99 and later do not support implicit function declarations

[kernel test robot <lkp@intel.com>]

tree:   https://git.kernel.org/pub/scm/linux/kernel/git/arnd/playground.git to-build
head:   b24255b1afbf1c9f6fd6e9baaa5ace64e4d2e94c
commit: 598ee66c1329c7278ca1fc694f112db6d9ec50e2 [6/9] atomic: Add option for weaker alignment check
config: arm64-allmodconfig (https://download.01.org/0day-ci/archive/20251015/202510150524.uUhfjhUU-lkp@intel.com/config)
compiler: clang version 19.1.7 (https://github.com/llvm/llvm-project cd708029e0b2869e80abe31ddb175f7c35361f90)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251015/202510150524.uUhfjhUU-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202510150524.uUhfjhUU-lkp@intel.com/

All errors (new ones prefixed by >>):

   In file included from kernel/bounds.c:13:
   In file included from include/linux/log2.h:12:
   In file included from include/linux/bitops.h:67:
   In file included from arch/arm64/include/asm/bitops.h:25:
   In file included from include/asm-generic/bitops/atomic.h:5:
   In file included from include/linux/atomic.h:82:
   In file included from include/linux/atomic/atomic-instrumented.h:17:
   In file included from include/linux/instrumented.h:11:
   In file included from include/linux/cache.h:6:
   In file included from include/vdso/cache.h:5:
>> arch/arm64/include/asm/cache.h:69:9: error: call to undeclared function '_test_bit'; ISO C99 and later do not support implicit function declarations [-Wimplicit-function-declaration]
      69 |         return test_bit(ICACHEF_ALIASING, &__icache_flags);
         |                ^
   include/linux/bitops.h:60:35: note: expanded from macro 'test_bit'
      60 | #define test_bit(nr, addr)              bitop(_test_bit, nr, addr)
         |                                               ^
   1 error generated.
   make[3]: *** [scripts/Makefile.build:182: kernel/bounds.s] Error 1
   make[3]: Target 'prepare' not remade because of errors.
   make[2]: *** [Makefile:1282: prepare0] Error 2
   make[2]: Target 'prepare' not remade because of errors.
   make[1]: *** [Makefile:248: __sub-make] Error 2
   make[1]: Target 'prepare' not remade because of errors.
   make: *** [Makefile:248: __sub-make] Error 2
   make: Target 'prepare' not remade because of errors.


vim +/_test_bit +69 arch/arm64/include/asm/cache.h

02f7760e6e5c3d Will Deacon 2017-03-10  62  
02f7760e6e5c3d Will Deacon 2017-03-10  63  /*
02f7760e6e5c3d Will Deacon 2017-03-10  64   * Whilst the D-side always behaves as PIPT on AArch64, aliasing is
02f7760e6e5c3d Will Deacon 2017-03-10  65   * permitted in the I-cache.
02f7760e6e5c3d Will Deacon 2017-03-10  66   */
02f7760e6e5c3d Will Deacon 2017-03-10  67  static inline int icache_is_aliasing(void)
02f7760e6e5c3d Will Deacon 2017-03-10  68  {
02f7760e6e5c3d Will Deacon 2017-03-10 @69  	return test_bit(ICACHEF_ALIASING, &__icache_flags);
02f7760e6e5c3d Will Deacon 2017-03-10  70  }
02f7760e6e5c3d Will Deacon 2017-03-10  71  

:::::: The code at line 69 was first introduced by commit
:::::: 02f7760e6e5c3d726cd9622749cdae17c571b9a3 arm64: cache: Merge cachetype.h into cache.h

:::::: TO: Will Deacon <will.deacon@arm.com>
:::::: CC: Catalin Marinas <catalin.marinas@arm.com>

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