From: Xie Yuanbin <qq570070308@gmail.com>
To: tglx@linutronix.de
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Subject: Re: [PATCH v3 3/3] Make finish_task_switch and its subfuncs inline in context switching
Date: Sat, 15 Nov 2025 23:09:28 +0800 [thread overview]
Message-ID: <20251115150928.649-1-qq570070308@gmail.com> (raw)
In-Reply-To: <87346gbd04.ffs@tglx>
On Fri, 14 Nov 2025 21:00:43 +0100, Thomas Gleixner wrote:
> What are subfuncs? This is not a SMS service. Use proper words and not
> made up abbreviations.
>
> Again you mark them __always_inline and not inline. Most of them are
> already 'inline'. Can you please precise in your wording?
>
> This really can go into the comment section below the first '---'
> separator. No point in having this in the change log.
Thanks for pointing it out, I will improve it in v4 patch.
>> After `finish_task_switch` is changed to an inline function, the number of
>> calls to the subfunctions (called by `finish_task_switch`) increases in
>> this translation unit due to the inline expansion of `finish_task_switch`.
>> Due to compiler optimization strategies, these functions may transition
>> from inline functions to non inline functions, which can actually lead to
>> performance degradation.
>
> I'm having a hard time to understand this word salad.
I think the description is very important here, because it explains why
it needs to make the subfunctions as __always_inline.
Where is difficult to understand specifically? Please point it out,
and I will improve the description in v4 patch. Thank you very much!
> What means (rdtsc)?
This is a high-precision timestamp acquisition method in x86.
The description here is not sufficient, thanks for pointing it out, I
will improve it in v4 patch.
> So the real benefit is observable when spectre_v2_user mitigations are
> enabled. You completely fail to explain that.
What kind of explanation is needed here?
```txt
When spectre_v2_user mitigation is enabled, kernel is likely to
preform branch prediction hardening inside switch_mm_irq_off, which can
drastically increase the branch prediction misses in subsequently
executed code.
On x86, this mitigation is enabled conditionally by default, but on other
architectures, for example arm32/aarch64, the mitigation may be fully
enabled by default.
`finish_task_switch` is right after `switch_mm_irq_off`, so makeing it
inline can achieve high performance benefits.
```
Is it ok? Thanks very much!
> bzImage size is completely irrelevant. What's interesting is how the
> size of the actual function changes.
I think the bzImage size is meaningful, at least for many embedded
devices. Due to compression algorithms, code size cannot directly reflect
to the compressed size.
Anyway, I will supplement the size of the .text section in the v4 patch.
Thanks very much!
Xie Yuanbin
prev parent reply other threads:[~2025-11-15 15:09 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-13 10:52 [PATCH v3 0/3] Optimize code generation during context switching Xie Yuanbin
2025-11-13 10:52 ` [PATCH v3 1/3] Make enter_lazy_tlb inline on x86 Xie Yuanbin
2025-11-13 11:02 ` Xie Yuanbin
2025-11-13 12:11 ` David Hildenbrand (Red Hat)
2025-11-14 19:42 ` Thomas Gleixner
2025-11-15 13:54 ` Xie Yuanbin
2025-11-13 10:52 ` [PATCH v3 2/3] Make raw_spin_rq_unlock inline Xie Yuanbin
2025-11-14 19:44 ` Thomas Gleixner
2025-11-15 14:01 ` Xie Yuanbin
2025-11-13 10:52 ` [PATCH v3 3/3] Make finish_task_switch and its subfuncs inline in context switching Xie Yuanbin
2025-11-14 20:00 ` Thomas Gleixner
2025-11-15 15:09 ` Xie Yuanbin [this message]
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