Re: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function.

[kernel test robot <lkp@intel.com>]

Hi Wenliang,

kernel test robot noticed the following build errors:

[auto build test ERROR on groeck-staging/hwmon-next]
[also build test ERROR on robh/for-next linus/master v6.18-rc6 next-20251118]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Wenliang-Yan/dt-bindings-hwmon-ti-ina3221-Add-SQ52210/20251118-205717
base:   https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-next
patch link:    https://lore.kernel.org/r/20251118125148.95603-7-wenliang202407%40163.com
patch subject: [PATCH v2 6/8] hwmon: (ina3221) Support for writing alert limit values and modify the 'ina3221_read_value' function.
config: arm-randconfig-002-20251119 (https://download.01.org/0day-ci/archive/20251119/202511191138.FRi6Ldng-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251119/202511191138.FRi6Ldng-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202511191138.FRi6Ldng-lkp@intel.com/

All errors (new ones prefixed by >>):

>> drivers/hwmon/ina3221.c:554:7: error: duplicate case value: 'hwmon_curr_lcrit' and 'hwmon_in_lcrit' both equal '4'
           case hwmon_in_lcrit:
                ^
   drivers/hwmon/ina3221.c:541:7: note: previous case defined here
           case hwmon_curr_lcrit:
                ^
   1 error generated.


vim +554 drivers/hwmon/ina3221.c

   507	
   508	static int sq52210_alert_limit_write(struct ina3221_data *ina, u32 attr, int channel, long val)
   509	{
   510		struct regmap *regmap = ina->regmap;
   511		int item = channel % INA3221_NUM_CHANNELS;
   512		u8 limit_reg;
   513		u32 alert_group, alert_mask = 0;
   514		int regval = 0;
   515		int ret;
   516	
   517		if (item >= ARRAY_SIZE(alert_groups) || val < 0)
   518			return -EINVAL;
   519	
   520		alert_group = alert_groups[item];
   521		limit_reg = limit_regs[item];
   522	
   523		/* Clear alerts for this channel group first */
   524		ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG, alert_group, 0);
   525		if (ret)
   526			return ret;
   527	
   528		/* Determine alert type and calculate register value */
   529		switch (attr) {
   530		/*
   531		 * The alert warning logic is implemented by comparing the limit register values
   532		 * with the corresponding alert source register values. Since the current register
   533		 * is a 15-bit signed register and the power register is a 16-bit unsigned
   534		 * register, but the lower 3 bits of the limit register default to 0, the lower
   535		 * 3 bits will be forced to 0 when setting SUL and POL warning values.
   536		 * Formula to convert register value:
   537		 *     bus_voltage: (regval / 8mV) << 3
   538		 *     current: (regval / current_lsb) & 0xfff8
   539		 *     power: (regval / current_lsb) & 0xfff8
   540		 */
   541		case hwmon_curr_lcrit:
   542			/* SUL: Shunt Under Limit - BIT(15), BIT(14), BIT(13) */
   543			alert_mask = BIT(15 - item);
   544			/* Current Register, signed register, result in mA */
   545			regval = DIV_ROUND_CLOSEST(val * 1000, ina->current_lsb_uA) & 0xfff8;
   546			regval = clamp_val(regval, -32760, 32760);
   547			break;
   548		case hwmon_in_crit:
   549			/* BOL: Bus Over Limit - BIT(12), BIT(11), BIT(10) */
   550			alert_mask = BIT(12 - item);
   551			/* Bus Register, signed register, result in mV */
   552			regval = clamp_val(val, -32760, 32760);
   553			break;
 > 554		case hwmon_in_lcrit:
   555			/* BUL: Bus Under Limit - BIT(9), BIT(8), BIT(7) */
   556			alert_mask = BIT(9 - item);
   557			/* Bus Register, signed register, result in mV */
   558			regval = clamp_val(val, -32760, 32760);
   559			break;
   560		case hwmon_power_crit:
   561			/* POL: Power Over Limit - BIT(6), BIT(5), BIT(4) */
   562			alert_mask = BIT(6 - item);
   563			/* Power Register, unsigned register, result in mW */
   564			regval = DIV_ROUND_CLOSEST(val * 1000, ina->power_lsb_uW) & 0xfff8;
   565			regval = clamp_val(regval, 0, 65528);
   566			break;
   567		default:
   568			/* For unsupported attributes, just clear the configuration */
   569			ina->alert_type_select &= ~alert_group;
   570			return -EOPNOTSUPP;
   571		}
   572	
   573		/* Write limit register value */
   574		ret = regmap_write(regmap, limit_reg, regval);
   575		if (ret)
   576			return ret;
   577	
   578		/* Update alert configuration if limit value is non-zero */
   579		if (regval) {
   580			ina->alert_type_select = (ina->alert_type_select & ~alert_group) | alert_mask;
   581			ret = regmap_update_bits(regmap, SQ52210_ALERT_CONFIG,
   582						alert_group, alert_mask);
   583		} else {
   584			ina->alert_type_select &= ~alert_group;
   585		}
   586	
   587		return ret;
   588	}
   589	

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