* Re: [PATCH net v2] net: dsa: mxl-gsw1xx: manually clear RANEG bit
[not found] <a90b206e9fd8e4248fd639afd5ae296454ac99b9.1765060046.git.daniel@makrotopia.org>
@ 2025-12-08 1:31 ` kernel test robot
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From: kernel test robot @ 2025-12-08 1:31 UTC (permalink / raw)
To: Daniel Golle, Hauke Mehrtens, Andrew Lunn, Vladimir Oltean,
David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Russell King, linux-kernel
Cc: llvm, oe-kbuild-all, netdev, Rasmus Villemoes,
Benny (Ying-Tsan) Weng, John Crispin
Hi Daniel,
kernel test robot noticed the following build errors:
[auto build test ERROR on net/main]
url: https://github.com/intel-lab-lkp/linux/commits/Daniel-Golle/net-dsa-mxl-gsw1xx-manually-clear-RANEG-bit/20251207-063852
base: net/main
patch link: https://lore.kernel.org/r/a90b206e9fd8e4248fd639afd5ae296454ac99b9.1765060046.git.daniel%40makrotopia.org
patch subject: [PATCH net v2] net: dsa: mxl-gsw1xx: manually clear RANEG bit
config: riscv-allyesconfig (https://download.01.org/0day-ci/archive/20251208/202512080800.2VZCNFnY-lkp@intel.com/config)
compiler: clang version 16.0.6 (https://github.com/llvm/llvm-project 7cbf1a2591520c2491aa35339f227775f4d3adf6)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251208/202512080800.2VZCNFnY-lkp@intel.com/reproduce)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512080800.2VZCNFnY-lkp@intel.com/
All errors (new ones prefixed by >>):
>> drivers/net/dsa/lantiq/mxl-gsw1xx.c:449:28: error: use of undeclared identifier 'gsw1xx_priv'
cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
^
1 error generated.
vim +/gsw1xx_priv +449 drivers/net/dsa/lantiq/mxl-gsw1xx.c
444
445 static void gsw1xx_pcs_an_restart(struct phylink_pcs *pcs)
446 {
447 struct gsw1xx_priv *priv = pcs_to_gsw1xx(pcs);
448
> 449 cancel_delayed_work_sync(&gsw1xx_priv->clear_raneg);
450
451 regmap_set_bits(priv->sgmii, GSW1XX_SGMII_TBI_ANEGCTL,
452 GSW1XX_SGMII_TBI_ANEGCTL_RANEG);
453
454 /* despite being documented as self-clearing, the RANEG bit
455 * sometimes remains set, preventing auto-negotiation from happening.
456 * MaxLinear advises to manually clear the bit after 10ms.
457 */
458 schedule_delayed_work(&priv->clear_raneg, msecs_to_jiffies(10));
459 }
460
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
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