[jcmvbkbc-xtensa:pr/24 1/1] arch/x86/kvm/emulate.c:1759:4: error: expected expression

[kernel test robot <lkp@intel.com>]

tree:   https://github.com/jcmvbkbc/linux-xtensa pr/24
head:   dcd699a99ce2f40e50263e0ec438e3b57b133598
commit: dcd699a99ce2f40e50263e0ec438e3b57b133598 [1/1] Fix potential vulnerability in cloned code (arch/x86/kvm/emulate.c)
config: x86_64-kexec (https://download.01.org/0day-ci/archive/20251222/202512220002.VT40yPyF-lkp@intel.com/config)
compiler: clang version 20.1.8 (https://github.com/llvm/llvm-project 87f0227cb60147a26a1eeb4fb06e3b505e9c7261)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251222/202512220002.VT40yPyF-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512220002.VT40yPyF-lkp@intel.com/

All error/warnings (new ones prefixed by >>):

>> arch/x86/kvm/emulate.c:1741:2: warning: '/*' within block comment [-Wcomment]
    1741 |         /*
         |         ^
>> arch/x86/kvm/emulate.c:1759:4: error: expected expression
    1759 |          */
         |           ^
   arch/x86/kvm/emulate.c:1760:2: error: expected expression
    1760 |         if (seg == VCPU_SREG_SS && selector == 3 &&
         |         ^
   1 warning and 2 errors generated.


vim +1759 arch/x86/kvm/emulate.c

  1733	
  1734	static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
  1735					   u16 selector, int seg)
  1736	{
  1737		u8 cpl = ctxt->ops->cpl(ctxt);
  1738	
  1739	
  1740		/*
> 1741		/*
  1742		 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
  1743		 * None of MOV, POP and LSS can load a NULL selector in CPL=3, but
  1744		 * they can load it at CPL<3 (Intel's manual says only LSS can,
  1745		 * they can load it at CPL<3 (Intel's manual says only LSS can,
  1746		 * but it's wrong).
  1747		 * but it's wrong).
  1748		 *
  1749		 *
  1750		 * However, the Intel manual says that putting IST=1/DPL=3 in
  1751		 * However, the Intel manual says that putting IST=1/DPL=3 in
  1752		 * an interrupt gate will result in SS=3 (the AMD manual instead
  1753		 * an interrupt gate will result in SS=3 (the AMD manual instead
  1754		 * says it doesn't), so allow SS=3 in __load_segment_descriptor
  1755		 * says it doesn't), so allow SS=3 in __load_segment_descriptor
  1756		 * and only forbid it here.
  1757		 * and only forbid it here.
  1758		 */
> 1759		 */
  1760		if (seg == VCPU_SREG_SS && selector == 3 &&
  1761		if (seg == VCPU_SREG_SS && selector == 3 &&
  1762		    ctxt->mode == X86EMUL_MODE_PROT64)
  1763		    ctxt->mode == X86EMUL_MODE_PROT64)
  1764			return emulate_exception(ctxt, GP_VECTOR, 0, true);
  1765			return emulate_exception(ctxt, GP_VECTOR, 0, true);
  1766	
  1767	
  1768		return __load_segment_descriptor(ctxt, selector, seg, cpl,
  1769						 X86_TRANSFER_NONE, NULL);
  1770	}
  1771	

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki