Re: [RFC PATCH] PCI: Work around CXL Port PM Init failure when ACS SV enabled

Re: [RFC PATCH] PCI: Work around CXL Port PM Init failure when ACS SV enabled

[kernel test robot]

Hi Fabio,

[This is a private test report for your RFC patch.]
kernel test robot noticed the following build warnings:

[auto build test WARNING on pci/next]
[also build test WARNING on pci/for-linus cxl/next linus/master v7.0-rc2 next-20260305]
[cannot apply to cxl/pending]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Fabio-M-De-Francesco/PCI-Work-around-CXL-Port-PM-Init-failure-when-ACS-SV-enabled/20260307-035826
base:   https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git next
patch link:    https://lore.kernel.org/r/20260306195232.388814-1-fabio.m.de.francesco%40linux.intel.com
patch subject: [RFC PATCH] PCI: Work around CXL Port PM Init failure when ACS SV enabled
config: loongarch-allnoconfig (https://download.01.org/0day-ci/archive/20260307/202603071429.J91G5AVd-lkp@intel.com/config)
compiler: clang version 23.0.0git (https://github.com/llvm/llvm-project c32caeec8158d634bb71ab8911a6031248b9fc47)
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20260307/202603071429.J91G5AVd-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202603071429.J91G5AVd-lkp@intel.com/

All warnings (new ones prefixed by >>):

>> drivers/pci/pci.c:4883:6: warning: no previous prototype for function 'cxl_sbr_masked' [-Wmissing-prototypes]
    4883 | bool cxl_sbr_masked(struct pci_dev *dev)
         |      ^
   drivers/pci/pci.c:4883:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
    4883 | bool cxl_sbr_masked(struct pci_dev *dev)
         | ^
         | static 
   1 warning generated.


vim +/cxl_sbr_masked +4883 drivers/pci/pci.c

  4882	
> 4883	bool cxl_sbr_masked(struct pci_dev *dev)
  4884	{
  4885		u16 dvsec, reg;
  4886		int rc;
  4887	
  4888		dvsec = cxl_port_dvsec(dev);
  4889		if (!dvsec)
  4890			return false;
  4891	
  4892		rc = pci_read_config_word(dev, dvsec + PCI_DVSEC_CXL_PORT_CTL, &reg);
  4893		if (rc || PCI_POSSIBLE_ERROR(reg))
  4894			return false;
  4895	
  4896		/*
  4897		 * Per CXL spec r3.1, sec 8.1.5.2, when "Unmask SBR" is 0, the SBR
  4898		 * bit in Bridge Control has no effect.  When 1, the Port generates
  4899		 * hot reset when the SBR bit is set to 1.
  4900		 */
  4901		if (reg & PCI_DVSEC_CXL_PORT_CTL_UNMASK_SBR)
  4902			return false;
  4903	
  4904		return true;
  4905	}
  4906	EXPORT_SYMBOL_NS_GPL(cxl_sbr_masked, "CXL");
  4907	

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