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charset=us-ascii tree: https://gitlab.com/stefandoesinger/zx297520-kernel dlink head: 7998b6e929bb20ed66acafa33720d8e3533e1598 commit: 43b934983d6f2811702f80419b92a1c62988fb7e [23/142] ARM: zte: HACK: Set up GICv3. config: arm-spear3xx_defconfig (https://download.01.org/0day-ci/archive/20261009/202610090931.MTCqZgr1-lkp@intel.com/config) compiler: clang version 24.0.0git (https://github.com/llvm/llvm-project 242243a5814307de825db3428662d67b064e2cbc) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261009/202610090931.MTCqZgr1-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202610090931.MTCqZgr1-lkp@intel.com/ All errors (new ones prefixed by >>): >> arch/arm/kernel/head.S:129:2: error: invalid instruction, any one of the following would fix this: mov r3, #0x131 @ non-secure ^ arch/arm/kernel/head.S:129:11: note: invalid operand for instruction mov r3, #0x131 @ non-secure ^ arch/arm/kernel/head.S:129:11: note: operand must be a register in range [r0, r15] mov r3, #0x131 @ non-secure ^ arch/arm/kernel/head.S:129:2: note: instruction requires: armv6t2 mov r3, #0x131 @ non-secure ^ vim +129 arch/arm/kernel/head.S 105 106 @ FIXME: This needs to go into the bootloader, it has no business being here. 107 @ zx297520v3 has essentially an ARMv8 CPU with a GICv3 and secure mode support, but there's 108 @ no ARM TrustZone firmware. So we have to set up the CPU and GIC according to arm64 boot 109 @ requirements specified in Documentation/arch/arm64/booting.rst. 110 @ Leave r0, r1 and r2 alone to preserve the DTB pointer. 111 112 @ This allows EL1 to handle ints hat are normally handled by EL2/3. 113 @ Detect sane bootloaders and skip the hack 114 ldr r3, =0xf2000000 115 ldr r3, [r3] 116 ldr r4, =(GICD_CTLR_ARE_NS | GICD_CTLR_DS) 117 cmp r3, r4 118 beq skip_zx_hack 119 ldr r3, =0xf2000000 120 str r4, [r3] 121 122 cps #MON_MODE 123 124 @ Work in non-secure physical addres space: SCR_EL3.NS = 1. At least the UART seems to 125 @ respond only to non-secure addresses. I have taken insipiration from Raspberry pi's 126 @ armstub7.S here. 127 @ 128 @ ARM docs say modify this bit in monitor mode only... > 129 mov r3, #0x131 @ non-secure 130 mcr p15, 0, r3, c1, c1, 0 131 132 @ AP_PPI_MODE_REG: Configure timer PPIs (10, 11, 13, 14) to active-low. 133 ldr r3, =0xF22020a8 134 ldr r4, =0x50 135 str r4, [r3] 136 ldr r3, =0xF22020ac 137 ldr r4, =0x14 138 str r4, [r3] 139 140 @ Enable EL access to ICC_SRE (bit 3, ICC_SRE_EL3.Enable). Enable system reg access to 141 @ GICv3 registers (bit 0, ICC_SRE_EL3.SRE). 142 mrc p15, 6, r3, c12, c12, 5 @ ICC_SRE_EL3 143 orr r3, #0x9 @ FIXME: No defines for SRE_EL3 values? 144 mcr p15, 6, r3, c12, c12, 5 145 mrc p15, 0, r3, c12, c12, 5 @ ICC_SRE_EL1 146 orr r3, #(ICC_SRE_EL1_SRE) 147 mcr p15, 0, r3, c12, c12, 5 148 149 @ Like ICC_SRE_EL3, enable non-secure access and allow register based access. 150 mrc p15, 4, r3, c12, c9, 5 @ ICC_SRE_EL2 aka ICC_HSRE 151 orr r3, r3, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE) 152 mcr p15, 4, r3, c12, c9, 5 153 isb 154 155 @ Back to SVC mode. TODO: Doesn't safe_svcmode_maskall do this for us anyway? 156 cps #SVC_MODE 157 skip_zx_hack: 158 159 @ ensure svc mode and all interrupts masked 160 safe_svcmode_maskall r9 161 162 mrc p15, 0, r9, c0, c0 @ get processor id 163 bl __lookup_processor_type @ r5=procinfo r9=cpuid 164 movs r10, r5 @ invalid processor (r5=0)? 165 THUMB( it eq ) @ force fixup-able long branch encoding 166 beq __error_p @ yes, error 'p' 167 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki