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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , David Wu , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui , Lukasz Luba , Maxime Chevallier Cc: llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, netdev@vger.kernel.org Subject: Re: [PATCH 07/27] clk: rockchip: Add RK3572 clock and reset support Message-ID: <202610221315.TGWtYMdM-lkp@intel.com> References: <20261022-add-board-ok3572-c-v1-7-0b0fd85a31ee@qq.com> X-Mailing-List: llvm@lists.linux.dev List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261022-add-board-ok3572-c-v1-7-0b0fd85a31ee@qq.com> Hi Cunhao, kernel test robot noticed the following build warnings: [auto build test WARNING on a804c5742bff224d4cb4d25dd383554d598be32b] url: https://github.com/intel-lab-lkp/linux/commits/Cunhao-Lu-via-B4-Relay/dt-bindings-clock-rockchip-Add-RK3572-CRU/20261022-001058 base: a804c5742bff224d4cb4d25dd383554d598be32b patch link: https://lore.kernel.org/r/20261022-add-board-ok3572-c-v1-7-0b0fd85a31ee%40qq.com patch subject: [PATCH 07/27] clk: rockchip: Add RK3572 clock and reset support config: arm-randconfig-1001-20261022 (https://download.01.org/0day-ci/archive/20261022/202610221315.TGWtYMdM-lkp@intel.com/config) compiler: clang version 21.1.8 (https://github.com/llvm/llvm-project 2078da43e25a4623cab2d0d60decddf709aaea28) reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20261022/202610221315.TGWtYMdM-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202610221315.TGWtYMdM-lkp@intel.com/ All warnings (new ones prefixed by >>): >> drivers/clk/rockchip/clk-rk3572.c:121:40: warning: implicit conversion from 'int' to 's16' (aka 'short') changes value from 47185 to -18351 [-Wconstant-conversion] 121 | RK3588_PLL_RATE(266580000, 1, 178, 4, 47185), | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~ drivers/clk/rockchip/clk.h:607:7: note: expanded from macro 'RK3588_PLL_RATE' 604 | .p = _p, \ | ~ 605 | .m = _m, \ 606 | .s = _s, \ 607 | .k = _k, \ | ^~ drivers/clk/rockchip/clk-rk3572.c:116:40: warning: implicit conversion from 'int' to 's16' (aka 'short') changes value from 52428 to -13108 [-Wconstant-conversion] 116 | RK3588_PLL_RATE(604800000, 1, 101, 2, 52428), | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~ drivers/clk/rockchip/clk.h:607:7: note: expanded from macro 'RK3588_PLL_RATE' 604 | .p = _p, \ | ~ 605 | .m = _m, \ 606 | .s = _s, \ 607 | .k = _k, \ | ^~ drivers/clk/rockchip/clk-rk3572.c:112:40: warning: implicit conversion from 'int' to 's16' (aka 'short') changes value from 43690 to -21846 [-Wconstant-conversion] 112 | RK3588_PLL_RATE(773000000, 2, 258, 2, 43690), | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~ drivers/clk/rockchip/clk.h:607:7: note: expanded from macro 'RK3588_PLL_RATE' 604 | .p = _p, \ | ~ 605 | .m = _m, \ 606 | .s = _s, \ 607 | .k = _k, \ | ^~ drivers/clk/rockchip/clk-rk3572.c:98:41: warning: implicit conversion from 'int' to 's16' (aka 'short') changes value from 52559 to -12977 [-Wconstant-conversion] 98 | RK3588_PLL_RATE(1186812000, 2, 198, 1, 52559), | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~ drivers/clk/rockchip/clk.h:607:7: note: expanded from macro 'RK3588_PLL_RATE' 604 | .p = _p, \ | ~ 605 | .m = _m, \ 606 | .s = _s, \ 607 | .k = _k, \ | ^~ drivers/clk/rockchip/clk-rk3572.c:97:41: warning: implicit conversion from 'int' to 's16' (aka 'short') changes value from 52581 to -12955 [-Wconstant-conversion] 97 | RK3588_PLL_RATE(1186814000, 2, 198, 1, 52581), | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~ drivers/clk/rockchip/clk.h:607:7: note: expanded from macro 'RK3588_PLL_RATE' 604 | .p = _p, \ | ~ 605 | .m = _m, \ 606 | .s = _s, \ 607 | .k = _k, \ | ^~ 5 warnings generated. vim +121 drivers/clk/rockchip/clk-rk3572.c 43 44 static struct rockchip_pll_rate_table rk3572_pll_rates[] = { 45 /* _mhz, _p, _m, _s, _k */ 46 RK3588_PLL_RATE(2520000000, 2, 210, 0, 0), 47 RK3588_PLL_RATE(2496000000, 2, 208, 0, 0), 48 RK3588_PLL_RATE(2472000000, 2, 206, 0, 0), 49 RK3588_PLL_RATE(2448000000, 2, 204, 0, 0), 50 RK3588_PLL_RATE(2424000000, 2, 202, 0, 0), 51 RK3588_PLL_RATE(2400000000, 2, 200, 0, 0), 52 RK3588_PLL_RATE(2376000000, 2, 198, 0, 0), 53 RK3588_PLL_RATE(2352000000, 2, 196, 0, 0), 54 RK3588_PLL_RATE(2328000000, 2, 194, 0, 0), 55 RK3588_PLL_RATE(2304000000, 2, 192, 0, 0), 56 RK3588_PLL_RATE(2280000000, 2, 190, 0, 0), 57 RK3588_PLL_RATE(2256000000, 2, 376, 1, 0), 58 RK3588_PLL_RATE(2232000000, 2, 372, 1, 0), 59 RK3588_PLL_RATE(2208000000, 2, 368, 1, 0), 60 RK3588_PLL_RATE(2184000000, 2, 364, 1, 0), 61 RK3588_PLL_RATE(2160000000, 2, 360, 1, 0), 62 RK3588_PLL_RATE(2136000000, 2, 356, 1, 0), 63 RK3588_PLL_RATE(2112000000, 2, 352, 1, 0), 64 RK3588_PLL_RATE(2088000000, 2, 348, 1, 0), 65 RK3588_PLL_RATE(2064000000, 2, 344, 1, 0), 66 RK3588_PLL_RATE(2040000000, 2, 340, 1, 0), 67 RK3588_PLL_RATE(2016000000, 2, 336, 1, 0), 68 RK3588_PLL_RATE(1992000000, 2, 332, 1, 0), 69 RK3588_PLL_RATE(1968000000, 2, 328, 1, 0), 70 RK3588_PLL_RATE(1944000000, 2, 324, 1, 0), 71 RK3588_PLL_RATE(1920000000, 2, 320, 1, 0), 72 RK3588_PLL_RATE(1896000000, 2, 316, 1, 0), 73 RK3588_PLL_RATE(1872000000, 2, 312, 1, 0), 74 RK3588_PLL_RATE(1848000000, 2, 308, 1, 0), 75 RK3588_PLL_RATE(1824000000, 2, 304, 1, 0), 76 RK3588_PLL_RATE(1800000000, 2, 300, 1, 0), 77 RK3588_PLL_RATE(1776000000, 2, 296, 1, 0), 78 RK3588_PLL_RATE(1752000000, 2, 292, 1, 0), 79 RK3588_PLL_RATE(1728000000, 2, 288, 1, 0), 80 RK3588_PLL_RATE(1704000000, 2, 284, 1, 0), 81 RK3588_PLL_RATE(1680000000, 2, 280, 1, 0), 82 RK3588_PLL_RATE(1656000000, 2, 276, 1, 0), 83 RK3588_PLL_RATE(1632000000, 2, 272, 1, 0), 84 RK3588_PLL_RATE(1608000000, 2, 268, 1, 0), 85 RK3588_PLL_RATE(1584000000, 2, 264, 1, 0), 86 RK3588_PLL_RATE(1560000000, 2, 260, 1, 0), 87 RK3588_PLL_RATE(1536000000, 2, 256, 1, 0), 88 RK3588_PLL_RATE(1512000000, 2, 252, 1, 0), 89 RK3588_PLL_RATE(1488000000, 2, 248, 1, 0), 90 RK3588_PLL_RATE(1464000000, 2, 244, 1, 0), 91 RK3588_PLL_RATE(1440000000, 2, 240, 1, 0), 92 RK3588_PLL_RATE(1416000000, 2, 236, 1, 0), 93 RK3588_PLL_RATE(1392000000, 2, 232, 1, 0), 94 RK3588_PLL_RATE(1320000000, 2, 220, 1, 0), 95 RK3588_PLL_RATE(1200000000, 2, 200, 1, 0), 96 RK3588_PLL_RATE(1188000000, 2, 198, 1, 0), 97 RK3588_PLL_RATE(1186814000, 2, 198, 1, 52581), 98 RK3588_PLL_RATE(1186812000, 2, 198, 1, 52559), 99 RK3588_PLL_RATE(1109000000, 3, 554, 2, 32767), 100 RK3588_PLL_RATE(1100000000, 3, 550, 2, 0), 101 RK3588_PLL_RATE(1051000000, 3, 525, 2, 32767), 102 RK3588_PLL_RATE(1008000000, 2, 336, 2, 0), 103 RK3588_PLL_RATE(1000000000, 3, 500, 2, 0), 104 RK3588_PLL_RATE(983040000, 4, 655, 2, 23592), 105 RK3588_PLL_RATE(955520000, 3, 478, 2, -15730), 106 RK3588_PLL_RATE(903168000, 6, 903, 2, 11009), 107 RK3588_PLL_RATE(900000000, 2, 300, 2, 0), 108 RK3588_PLL_RATE(816000000, 2, 272, 2, 0), 109 RK3588_PLL_RATE(786432000, 2, 262, 2, 9437), 110 RK3588_PLL_RATE(786000000, 1, 131, 2, 0), 111 RK3588_PLL_RATE(785560000, 3, 393, 2, -14419), 112 RK3588_PLL_RATE(773000000, 2, 258, 2, 43690), 113 RK3588_PLL_RATE(722534400, 8, 963, 2, 24850), 114 RK3588_PLL_RATE(697000000, 2, 232, 2, 21845), 115 RK3588_PLL_RATE(610400000, 3, 305, 2, 13107), 116 RK3588_PLL_RATE(604800000, 1, 101, 2, 52428), 117 RK3588_PLL_RATE(600000000, 2, 200, 2, 0), 118 RK3588_PLL_RATE(594000000, 2, 198, 2, 0), 119 RK3588_PLL_RATE(408000000, 2, 272, 3, 0), 120 RK3588_PLL_RATE(312000000, 2, 208, 3, 0), > 121 RK3588_PLL_RATE(266580000, 1, 178, 4, 47185), 122 RK3588_PLL_RATE(216000000, 2, 288, 4, 0), 123 RK3588_PLL_RATE(96000000, 2, 256, 5, 0), 124 { /* sentinel */ }, 125 }; 126 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki