From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24345625 for ; Tue, 26 Apr 2022 10:28:45 +0000 (UTC) X-UUID: 162355498c0b48f2b1df6850e9fcc7b6-20220426 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:51a7fbd9-65de-4ec1-bb7b-d6919820e1e8,OB:0,LO B:0,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:53,FILE:0,RULE:Release_Ham,ACT ION:release,TS:61 X-CID-INFO: VERSION:1.1.4,REQID:51a7fbd9-65de-4ec1-bb7b-d6919820e1e8,OB:0,LOB: 0,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:53,FILE:0,RULE:Spam_GS981B3D,ACT ION:quarantine,TS:61 X-CID-META: VersionHash:faefae9,CLOUDID:bc09c02e-6199-437e-8ab4-9920b4bc5b76,C OID:01946d09fe8b,Recheck:0,SF:13|15|28|16|19|48,TC:nil,Content:0,EDM:-3,Fi le:nil,QS:0,BEC:nil X-UUID: 162355498c0b48f2b1df6850e9fcc7b6-20220426 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1132310296; Tue, 26 Apr 2022 18:28:36 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 26 Apr 2022 18:28:34 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Tue, 26 Apr 2022 18:28:34 +0800 Message-ID: <2e336c54b07cf5b661fd4a613545a932bca792fb.camel@mediatek.com> Subject: Re: [PATCH v17 13/21] drm/mediatek: add display merge async reset control From: Nancy.Lin To: Philipp Zabel , Rob Herring , Matthias Brugger , Chun-Kuang Hu , , AngeloGioacchino Del Regno , CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , "jason-jh . lin" , Yongqiang Niu , , , , , , , , Date: Tue, 26 Apr 2022 18:28:34 +0800 In-Reply-To: References: <20220416020749.29010-1-nancy.lin@mediatek.com> <20220416020749.29010-14-nancy.lin@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Hi Philipp, Thanks for the review. On Mon, 2022-04-25 at 11:58 +0200, Philipp Zabel wrote: > On Sa, 2022-04-16 at 10:07 +0800, Nancy.Lin wrote: > > Add merge async reset control in mtk_merge_stop. Async hw doesn't > > do self > > reset on each sof signal(start of frame), so need to reset the > > async to > > clear the hw status for the next merge start. > > > > Signed-off-by: Nancy.Lin > > Reviewed-by: CK Hu > > Reviewed-by: AngeloGioacchino Del Regno < > > angelogioacchino.delregno@collabora.com> > > --- > > drivers/gpu/drm/mediatek/mtk_disp_merge.c | 4 ++++ > > 1 file changed, 4 insertions(+) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c > > b/drivers/gpu/drm/mediatek/mtk_disp_merge.c > > index 9dca145cfb71..177473fa8160 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_disp_merge.c > > +++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c > > @@ -8,6 +8,7 @@ > > #include > > #include > > #include > > +#include > > #include > > > > > > > > > > #include "mtk_drm_ddp_comp.h" > > @@ -79,6 +80,9 @@ void mtk_merge_stop(struct device *dev) > > struct mtk_disp_merge *priv = dev_get_drvdata(dev); > > > > > > > > > > mtk_merge_stop_cmdq(dev, NULL); > > + > > + if (priv->async_clk) > > + device_reset_optional(dev); > > To avoid the overhead of looking up the reset control in the device > tree every time, it would be better to request a reset control during > probe using devm_reset_control_get_optional_exclusive(). Here you'd > just call reset_control_reset(). > > regards > Philipp OK. I will refine it in the next revision. Regards, Nancy