From: Matthias Brugger <matthias.bgg@gmail.com>
To: "Nancy.Lin" <nancy.lin@mediatek.com>,
Rob Herring <robh+dt@kernel.org>,
Chun-Kuang Hu <chunkuang.hu@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
wim@linux-watchdog.org,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
linux@roeck-us.net, nfraprado@collabora.com
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
"jason-jh . lin" <jason-jh.lin@mediatek.com>,
Yongqiang Niu <yongqiang.niu@mediatek.com>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org,
dri-devel@lists.freedesktop.org, llvm@lists.linux.dev,
singo.chang@mediatek.com,
Project_Global_Chrome_Upstream_Group@mediatek.com
Subject: Re: [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1
Date: Tue, 8 Nov 2022 18:46:51 +0100 [thread overview]
Message-ID: <32ae4104-673b-1b34-5efb-dc1317e80530@gmail.com> (raw)
In-Reply-To: <20221107072243.15748-7-nancy.lin@mediatek.com>
On 07/11/2022 08:22, Nancy.Lin wrote:
> Add four mmsys config APIs. The config APIs are used for config
> mmsys reg. Some mmsys regs need to be set according to the
> HW engine binding to the mmsys simultaneously.
>
> 1. mtk_mmsys_merge_async_config: config merge async width/height.
> async is used for cross-clock domain synchronization.
> 2. mtk_mmsys_hdr_confing: config hdr backend async width/height.
> 3. mtk_mmsys_mixer_in_config and mtk_mmsys_mixer_in_config:
> config mixer related settings.
>
> Signed-off-by: Nancy.Lin <nancy.lin@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Reviewed-by: CK Hu <ck.hu@mediatek.com>
> Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> Tested-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Not something we need to fix in this series, but it would make sense instead of
adding all the EXPORTS to pass the functions as callbacks in the
platform_device_register_data. But I realize you don't pass the VDOSYS number to
the DRM driver to distinguish between the different MMSYS devices that created
the platform device. I hadn't had a deep look on the DRM implementation but I
suppose it will be challenge...
Regards,
Matthias
> ---
> drivers/soc/mediatek/mt8195-mmsys.h | 6 +++++
> drivers/soc/mediatek/mtk-mmsys.c | 35 ++++++++++++++++++++++++++
> include/linux/soc/mediatek/mtk-mmsys.h | 9 +++++++
> 3 files changed, 50 insertions(+)
>
> diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
> index fd7b455bd675..454944a9409c 100644
> --- a/drivers/soc/mediatek/mt8195-mmsys.h
> +++ b/drivers/soc/mediatek/mt8195-mmsys.h
> @@ -75,6 +75,12 @@
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << 16)
> #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE (3 << 16)
>
> +#define MT8195_VDO1_MERGE0_ASYNC_CFG_WD 0xe30
> +#define MT8195_VDO1_HDRBE_ASYNC_CFG_WD 0xe70
> +#define MT8195_VDO1_HDR_TOP_CFG 0xd00
> +#define MT8195_VDO1_MIXER_IN1_ALPHA 0xd30
> +#define MT8195_VDO1_MIXER_IN1_PAD 0xd40
> +
> #define MT8195_VDO1_VPP_MERGE0_P0_SEL_IN 0xf04
> #define MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0 1
>
> diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
> index 73c8bd27e6ae..6040a3cff6f8 100644
> --- a/drivers/soc/mediatek/mtk-mmsys.c
> +++ b/drivers/soc/mediatek/mtk-mmsys.c
> @@ -137,6 +137,41 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
> }
> EXPORT_SYMBOL_GPL(mtk_mmsys_ddp_disconnect);
>
> +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height)
> +{
> + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MERGE0_ASYNC_CFG_WD + 0x10 * idx,
> + ~0, height << 16 | width);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_merge_async_config);
> +
> +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height)
> +{
> + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_HDRBE_ASYNC_CFG_WD, ~0,
> + be_height << 16 | be_width);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_hdr_config);
> +
> +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
> + u8 mode, u32 biwidth)
> +{
> + struct mtk_mmsys *mmsys = dev_get_drvdata(dev);
> +
> + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_ALPHA + (idx - 1) * 4, ~0,
> + alpha << 16 | alpha);
> + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_HDR_TOP_CFG, BIT(19 + idx),
> + alpha_sel << (19 + idx));
> + mtk_mmsys_update_bits(mmsys, MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
> + GENMASK(31, 16) | GENMASK(1, 0), biwidth << 16 | mode);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_config);
> +
> +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap)
> +{
> + mtk_mmsys_update_bits(dev_get_drvdata(dev), MT8195_VDO1_MIXER_IN1_PAD + (idx - 1) * 4,
> + BIT(4), channel_swap << 4);
> +}
> +EXPORT_SYMBOL_GPL(mtk_mmsys_mixer_in_channel_swap);
> +
> void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val)
> {
> if (val)
> diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
> index 127f1b888ace..a4708859c188 100644
> --- a/include/linux/soc/mediatek/mtk-mmsys.h
> +++ b/include/linux/soc/mediatek/mtk-mmsys.h
> @@ -75,4 +75,13 @@ void mtk_mmsys_ddp_disconnect(struct device *dev,
>
> void mtk_mmsys_ddp_dpi_fmt_config(struct device *dev, u32 val);
>
> +void mtk_mmsys_merge_async_config(struct device *dev, int idx, int width, int height);
> +
> +void mtk_mmsys_hdr_config(struct device *dev, int be_width, int be_height);
> +
> +void mtk_mmsys_mixer_in_config(struct device *dev, int idx, bool alpha_sel, u16 alpha,
> + u8 mode, u32 biwidth);
> +
> +void mtk_mmsys_mixer_in_channel_swap(struct device *dev, int idx, bool channel_swap);
> +
> #endif /* __MTK_MMSYS_H */
next prev parent reply other threads:[~2022-11-08 17:46 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-07 7:22 [PATCH v28 00/11] Add MediaTek SoC(vdosys1) support for mt8195 Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 01/11] dt-bindings: arm: mediatek: mmsys: add vdosys1 compatible for MT8195 Nancy.Lin
2022-11-08 17:46 ` Matthias Brugger
[not found] ` <f6d7eaa0b7e2a3ed6567692616ebc1304500806c.camel@mediatek.com>
2022-11-10 13:10 ` Matthias Brugger
[not found] ` <de21390898759ce979da8d2ae76a93982f59c149.camel@mediatek.com>
2022-11-22 15:48 ` Matthias Brugger
2022-11-23 16:06 ` Krzysztof Kozlowski
2022-11-07 7:22 ` [PATCH v28 02/11] dt-bindings: reset: mt8195: add vdosys1 reset control bit Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 03/11] soc: mediatek: add mtk-mmsys ethdr and mdp_rdma components Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 04/11] soc: mediatek: add mtk-mmsys support for mt8195 vdosys1 Nancy.Lin
2022-11-08 17:46 ` Matthias Brugger
2022-11-08 19:10 ` Nícolas F. R. A. Prado
2022-11-09 11:18 ` Matthias Brugger
2022-11-07 7:22 ` [PATCH v28 05/11] soc: mediatek: refine code to use mtk_mmsys_update_bits API Nancy.Lin
2022-11-08 17:37 ` Matthias Brugger
2022-11-08 19:43 ` Nícolas F. R. A. Prado
2022-11-10 13:12 ` Matthias Brugger
2022-12-01 11:44 ` Chen-Yu Tsai
2022-11-07 7:22 ` [PATCH v28 06/11] soc: mediatek: add mtk-mmsys config API for mt8195 vdosys1 Nancy.Lin
2022-11-08 17:46 ` Matthias Brugger [this message]
2022-11-07 7:22 ` [PATCH v28 07/11] soc: mediatek: add cmdq support of " Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 08/11] soc: mediatek: mmsys: add mmsys for support 64 reset bits Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 09/11] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 10/11] soc: mediatek: add mtk-mutex component - dp_intf1 Nancy.Lin
2022-11-07 7:22 ` [PATCH v28 11/11] soc: mediatek: add mtk-mutex support for mt8195 vdosys1 Nancy.Lin
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