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From: Ethan Zhao <haifeng.zhao@linux.intel.com>
To: Zhou Shengqing <zhoushengqing@ttyinfo.com>
Cc: helgaas@kernel.org, linux-kernel@vger.kernel.org,
	linux-pci@vger.kernel.org, lkp@intel.com, llvm@lists.linux.dev,
	oe-kbuild-all@lists.linux.dev
Subject: Re: [PATCH v4] Subject: PCI: Enable io space 1k granularity for intel cpu root port
Date: Wed, 24 Jul 2024 13:39:45 +0800	[thread overview]
Message-ID: <48373ac6-574b-4f72-b4f1-ddb7de8a5107@linux.intel.com> (raw)
In-Reply-To: <20240724033829.4724-1-zhoushengqing@ttyinfo.com>

On 7/24/2024 11:38 AM, Zhou Shengqing wrote:
>> On 7/23/2024 4:04 PM, Zhou Shengqing wrote:
>>>> I think this has potential.  Can you include a more complete citation
>>>> for the Intel spec?  Complete name, document number if available,
>>>> revision, section?  Hopefully it's publically available?
>>> Most of intel CPU EDS specs are under NDA. But you can refer to
>>> https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-e5-v2-datasheet-vol-2.pdf
>>> keyword:"EN1K".
>>> ...
>>>
>>> 	while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, 0x09a2, d))) {
>>> 		if (pci_domain_nr(d->bus) == pci_domain_nr(dev->bus)) {
>> Perhaps it is enough to check if the 0x09a2 VT-d and the rootport are on the smae bus
>> e.g. On my SPR, domain 0000
> Thank you for your comment.
>
> Do you mean it shoud be like this?
>
> 	while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, 0x09a2, d))) {
> 		if (d->bus->number == dev->bus->number) {
> 			pci_read_config_word(d, 0x1c0, &en1k);
> 			if (en1k & 0x4) {
> 				pci_info(dev, "1K I/O windows enabled per %s EN1K setting\n", pci_name(d));
> 				dev->io_window_1k = 1;
> 			}
> 		}
> 	}
>
>> 00:00.0 System peripheral: Intel Corporation Device 09a2 (rev 20)
>> 00:0f.0 PCI bridge: Intel Corporation Device 1bbf (rev 10) (prog-if 00 [Normal decode])
>>
>>    
>> 15:00.0 System peripheral: Intel Corporation Device 09a2 (rev 20)
>> 15:01.0 PCI bridge: Intel Corporation Device 352a (rev 04) (prog-if 00 [Normal decode])
>>
>> and if you check domain number only, they might sit on different bus, perhaps that
>> would make thing complex, could you make sure the VT-d is on the upstream bus of the
>> bridge ?
> I checked it on ICX SPR EMR GNR, VT-d is always on the same bus with root port,
> and VT-d device and function number is always 0.

Yes, every VT-d instance in the root complex and the root port integrated are
on the same bus. and VT-d is the first device of that bus.

The EDS doesn't say if there is exception one of the VT-d instances in an
system its EN1K wasn't set while others were set, vice vesa. so I suggest
just check the VT-d and then set the root port's io_windows_1k of the same bus.

Hope that works for your case.


Thanks,
Ethan

>
> Please let me know if further modifications are needed.
>
>> Thanks,
>> Ethan

  reply	other threads:[~2024-07-24  5:39 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <20240621020608.28964-1-zhoushengqing@ttyinfo.com>
2024-06-26 10:09 ` [PATCH] PCI: Enable io space 1k granularity for intel cpu root port kernel test robot
2024-06-26 11:19   ` [PATCH v2] [PATCH v2] " Zhou Shengqing
2024-06-26 15:26     ` Bjorn Helgaas
2024-06-27  0:58       ` [PATCH v3] " Zhou Shengqing
2024-06-29 21:34         ` Bjorn Helgaas
2024-06-30  2:52           ` Re: [PATCH] " Zhou Shengqing
2024-07-01 21:06             ` Bjorn Helgaas
2024-07-02  3:56               ` [PATCH v4] Subject: " Zhou Shengqing
2024-07-12 18:48                 ` Bjorn Helgaas
2024-07-23  8:04                   ` Zhou Shengqing
2024-07-24  2:34                     ` Ethan Zhao
2024-07-24  3:38                       ` Zhou Shengqing
2024-07-24  5:39                         ` Ethan Zhao [this message]
2024-07-24  6:35                           ` [PATCH v4] " Zhou Shengqing
2024-07-24  7:51                             ` Ethan Zhao
2024-07-25  7:44                               ` Zhou Shengqing
2024-07-26  2:27                                 ` Ethan Zhao
2024-07-02  5:49               ` Re: Re: [PATCH] PCI: Enable io space 1k granularity for Zhou Shengqing

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