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Mon, 17 Aug 2026 22:10:36 -0700 (PDT) X-Received: by 2002:a05:6a00:188b:b0:845:e8b9:347 with SMTP id d2e1a72fcca58-84fddfe099cmr29499576b3a.13.1787029835654; Mon, 17 Aug 2026 22:10:35 -0700 (PDT) Received: from [10.219.56.166] ([202.46.23.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-851b6ff2232sm1015652b3a.52.2026.08.17.22.10.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 17 Aug 2026 22:10:35 -0700 (PDT) Message-ID: <89ec74da-15ed-4278-b651-5c753fa4f146@oss.qualcomm.com> Date: Tue, 18 Aug 2026 10:40:25 +0530 Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 05/15] iommu: Add QDA compute context bank bus to iommu_buses To: Jason Gunthorpe Cc: Oded Gabbay , Jonathan Corbet , Shuah Khan , Randy Dunlap , Nathan Chancellor , Nick Desaulniers , Bill Wendling , Justin Stitt , "Joerg Roedel (AMD)" , Will Deacon , Robin Murphy , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?UTF-8?Q?Christian_K=C3=B6nig?= , Bharath Kumar , Chenna Kesava Raju , srinivas.kandagatla@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-arm-msm@vger.kernel.org, llvm@lists.linux.dev, iommu@lists.linux.dev, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org References: <20260817-qda-v2-v2-0-69a02e9090d4@oss.qualcomm.com> <20260817-qda-v2-v2-5-69a02e9090d4@oss.qualcomm.com> <20260817134416.GA1415075@ziepe.ca> Content-Language: en-US From: Ekansh Gupta In-Reply-To: <20260817134416.GA1415075@ziepe.ca> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Info: AW1haW4tMjYwODE4MDAzNiBTYWx0ZWRfXzUOmz12s545b YtEuygPuRGAvcsWK0EwxjDMF0AeNo1/dBJq1m0HJsUePjRamOEZtSUqDxsy1MAKZWYFdY0f2PoW ymdP8jKar67jEJbHrlHGh9kMgls3bW0= X-Authority-Analysis: v=2.4 cv=VuITxe2n c=1 sm=1 tr=0 ts=6a83e94d cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=j4ogTh8yFefVWWEFDRgCtg==:17 a=IkcTkHD0fZMA:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=VwQbUJbxAAAA:8 a=UlZBYPnkdO8YS_jrOJUA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: IHsOthFhTumQeDLVfcZ0c8C9NOTRtlbN X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODE4MDAzNiBTYWx0ZWRfX6K2p9KiZcT1J +0dCwd4M+y1qvLDI5pUWWM11W7PMwyOK+cmcHAozYHs6tYQQGtIaA5KJd2ALhNFBUQGdbBov7xY 5GLsyDOmojGD//08FGTOn65CkP5TXkrPUp6rbpdXBTl2Ku/9LHVJ0Pk4ZZ2tMDeMTdeZLPbKOz7 niKHVBmdbP6Ds5sZ5pfA3BiEn0kv2kAswtgYR77TzHaRqdajraHyGe+1LcrpViL73qUtZ7TOz68 SinXxCGOk7riP7ZHKweIpGBTFasVzz19ijKG//01cGfRnAyzmE3v0GjQXsXWWrGNxC+xFTXsvKI 88N3lsTtwTn+ffmUckjxGF1tgLLTrMWJchu+V3/P9Fk2JcL0ZzmCSwgeF5j4eqy1Dzm7CU2XUaE ub5cRnA+SYDGSWZfWZUoqwbatPHq1DdpX0zcUotbszVoPGSiWb/8ScNIYUpaKc79AUi+FLM7u48 aCTRADFSjm1xUAQxWfw== X-Proofpoint-ORIG-GUID: IHsOthFhTumQeDLVfcZ0c8C9NOTRtlbN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-17_04,2026-08-12_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 impostorscore=0 lowpriorityscore=0 bulkscore=0 malwarescore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608180036 On 17-08-2026 19:14, Jason Gunthorpe wrote: > On Mon, Aug 17, 2026 at 10:17:40AM +0530, Ekansh Gupta wrote: >> Register the QDA compute context bank bus (qda-compute-cb) with the >> IOMMU subsystem by adding it to the iommu_buses[] array. >> >> The QDA driver creates synthetic devices on this bus to represent >> IOMMU context banks (CBs). Each CB device needs its own IOMMU domain >> so that the DSP memory manager can enforce per-session address space >> isolation. Without this registration, the IOMMU subsystem does not >> probe CB devices for IOMMU groups and of_dma_configure() in the bus >> dma_configure callback has no IOMMU domain to attach to. > > I didn't notice a clear explanation of the proposed DT schema for this The context banks are described in DT as child nodes of the fastrpc RPMsg endpoint with compatible "qcom,fastrpc-compute-cb" and a `reg` property for the stream ID, this is the existing binding in Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml. QDA reuses this schema unchanged. > > But it looks awfully similar to the other driver that was creating a > kernel synthetic bus for actual real HW, that wasn't well liked. > > What is this for? Why can't you have a normal DT binding for the > iommu with normal devices? The CB child nodes are not separate addressable hardware — they are SMMU stream-ID assignments described as sub-resources of the parent DSP interface. Using platform devices for them was explicitly rejected by Greg KH [1] and subsequently using a generic shared bus in drivers/base/ was also rejected [2]. Greg's conclusion was that each driver needing this pattern should have its own custom bus type. That is exactly what QDA does: the qda-compute-cb bus is a per-driver bus type with a dma_configure callback, following the same pattern as the existing host1x_context_device_bus_type that has been in the iommu_buses[] array since 2021. The bus creates devices synchronously in probe, calls of_dma_configure() via its bus callback so the IOMMU subsystem probes them normally, and tears them down on remove. [1] https://lore.kernel.org/all/2025062434-reviving-grumble-1e53@gregkh/ [2] https://lore.kernel.org/all/2026042442-luxurious-antonym-f20c@gregkh/ //Ekansh> > Jason