From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C6FD120F7 for ; Wed, 4 May 2022 05:37:28 +0000 (UTC) X-UUID: 1e679e43cb5644039d343a85be615c3c-20220504 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:1ffa0ec7-d6d6-4706-816b-0fe6615d196e,OB:0,LO B:0,IP:0,URL:8,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:8 X-CID-META: VersionHash:faefae9,CLOUDID:43f2a22f-6199-437e-8ab4-9920b4bc5b76,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 1e679e43cb5644039d343a85be615c3c-20220504 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1763053625; Wed, 04 May 2022 13:37:22 +0800 Received: from mtkmbs07n1.mediatek.inc (172.21.101.16) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.3; Wed, 4 May 2022 13:37:21 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs07n1.mediatek.inc (172.21.101.16) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Wed, 4 May 2022 13:37:20 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.3 via Frontend Transport; Wed, 4 May 2022 13:37:20 +0800 Message-ID: <9d2ec46ac35cb638d668dbffa2e6df03f6d18a83.camel@mediatek.com> Subject: Re: [PATCH v19 10/25] soc: mediatek: mmsys: add reset control for MT8195 vdosys1 From: CK Hu To: Nancy.Lin , Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , , AngeloGioacchino Del Regno , CC: , , Yongqiang Niu , David Airlie , "jason-jh . lin" , , , Nick Desaulniers , , , "Nathan Chancellor" , , Date: Wed, 4 May 2022 13:37:20 +0800 In-Reply-To: <20220503102345.22817-11-nancy.lin@mediatek.com> References: <20220503102345.22817-1-nancy.lin@mediatek.com> <20220503102345.22817-11-nancy.lin@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Hi, Nancy: On Tue, 2022-05-03 at 18:23 +0800, Nancy.Lin wrote: > MT8195 vdosys1 has more than 32 reset bits and a different reset base > than other chips. Add the number of reset bits and reset base in > mmsys > private data. Reviewed-by: CK Hu > > Signed-off-by: Nancy.Lin > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- > drivers/soc/mediatek/mt8195-mmsys.h | 1 + > drivers/soc/mediatek/mtk-mmsys.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/drivers/soc/mediatek/mt8195-mmsys.h > b/drivers/soc/mediatek/mt8195-mmsys.h > index 454944a9409c..a6652ae63431 100644 > --- a/drivers/soc/mediatek/mt8195-mmsys.h > +++ b/drivers/soc/mediatek/mt8195-mmsys.h > @@ -75,6 +75,7 @@ > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0 (2 << > 16) > #define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE > (3 << 16) > > +#define MT8195_VDO1_SW0_RST_B > 0x1d0 > #define MT8195_VDO1_MERGE0_ASYNC_CFG_WD > 0xe30 > #define MT8195_VDO1_HDRBE_ASYNC_CFG_WD > 0xe70 > #define MT8195_VDO1_HDR_TOP_CFG > 0xd00 > diff --git a/drivers/soc/mediatek/mtk-mmsys.c > b/drivers/soc/mediatek/mtk-mmsys.c > index 6600185dd9a4..d6ea1b0ac2de 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -153,6 +153,8 @@ static const struct mtk_mmsys_driver_data > mt8195_vdosys1_driver_data = { > .clk_driver = "clk-mt8195-vdo1", > .routes = mmsys_mt8195_vdo1_routing_table, > .num_routes = ARRAY_SIZE(mmsys_mt8195_vdo1_routing_table), > + .sw0_rst_offset = MT8195_VDO1_SW0_RST_B, > + .num_resets = 64, > }; > > static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {