From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ACD3E2F22 for ; Wed, 19 Oct 2022 13:11:10 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 39E03C433D6; Wed, 19 Oct 2022 13:11:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1666185070; bh=wY1M4RkPxwgRgjYuzUK2ZTBXoD9/bIiPor4ikkDS9K4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=cc2gVFT+bbsm/hjhbo63RI4Q97w5HISjEMDg1F1wGD0JqNeKSpajr0PR2+d6sqOlB InKbG5krytIlt98zeDYQCEMrOx1MbEG1heA3WiaiTRdSnKpkU5f0nPIYNuDUZk5M+r uGDekJCYfnGda1Z9yq+5qLOvGbVFec8Bn+6nXljE2gmpsT2spwJo3vgECfjRxkERFS Um63BWHI3XZm+xp+0de5g2HgUYbFktmPFCcdWRlKpiwyIfTq0AztzyF+t7jDoeUIat zvAP+6Jle1C1OHIg6GR+4NtI3l0IrMBzaIW5a33hFFCOkYhHpShcUA1LkZJ0LMNYXV BTjVThuiLYziQ== Date: Wed, 19 Oct 2022 21:01:32 +0800 From: Jisheng Zhang To: Guo Ren Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Nathan Chancellor , Nick Desaulniers , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, llvm@lists.linux.dev Subject: Re: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp Message-ID: References: <20220928162007.3791-1-jszhang@kernel.org> <20220928162007.3791-5-jszhang@kernel.org> Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: On Wed, Oct 19, 2022 at 10:55:09AM +0800, Guo Ren wrote: > On Fri, Sep 30, 2022 at 12:11 AM Jisheng Zhang wrote: > > > > On Thu, Sep 29, 2022 at 11:59:00AM +0800, Guo Ren wrote: > > > On Thu, Sep 29, 2022 at 12:29 AM Jisheng Zhang wrote: > > > > > > > > Consolidate the saving/restoring GPs(except ra, sp and tp) into > > > > save_gp/restore_gp macro. > > > > > > > > No functional change intended. > > > > > > > > Signed-off-by: Jisheng Zhang > > > > --- > > > > arch/riscv/include/asm/asm.h | 65 +++++++++++++++++++++++++ > > > > arch/riscv/kernel/entry.S | 87 ++-------------------------------- > > > > arch/riscv/kernel/mcount-dyn.S | 58 +---------------------- > > > > 3 files changed, 70 insertions(+), 140 deletions(-) > > > > > > > > diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h > > > > index 1b471ff73178..2f3b49536e9d 100644 > > > > --- a/arch/riscv/include/asm/asm.h > > > > +++ b/arch/riscv/include/asm/asm.h > > > > @@ -68,6 +68,7 @@ > > > > #endif > > > > > > > > #ifdef __ASSEMBLY__ > > > > +#include > > > > > > > > /* Common assembly source macros */ > > > > > > > > @@ -80,6 +81,70 @@ > > > > .endr > > > > .endm > > > > > > > > + /* save all GPs except ra, sp and tp */ > > > > + .macro save_gp > > > How about leave x3(gp) out of the macro, and define: > > > .marco save_from_x5_to_x31 > > > .marco restore_from_x5_to_x31 > > > > Good idea, will do in next version. > > Where is the next version? > > I want to involve the patch in my generic entry series, it would help > in the coding convention of the entry code. Hi, Here is the v3: https://lore.kernel.org/linux-riscv/20221003102921.3973-1-jszhang@kernel.org/T/#t thanks very much