tree:   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/ci.git arm64-sysreg-gen-4
head:   033a9c641ed02d565771b605ce223a217a78ba5b
commit: 4c58057614042c492fca23584e04c8bf2cf3a0f8 [11/28] arm64/sysreg: Standardise naming for ID_AA64MMFR2_EL1.VARange
config: arm64-buildonly-randconfig-r004-20220818
compiler: clang version 16.0.0 (https://github.com/llvm/llvm-project aed5e3bea138ce581d682158eb61c27b3cfdd6ec)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://git.kernel.org/pub/scm/linux/kernel/git/broonie/ci.git/commit/?id=4c58057614042c492fca23584e04c8bf2cf3a0f8
        git remote add broonie-ci https://git.kernel.org/pub/scm/linux/kernel/git/broonie/ci.git
        git fetch --no-tags broonie-ci arm64-sysreg-gen-4
        git checkout 4c58057614042c492fca23584e04c8bf2cf3a0f8
        # save the config file
        mkdir build_dir && cp config build_dir/.config
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash arch/arm64/

If you fix the issue, kindly add following tag where applicable
Reported-by: kernel test robot <lkp@intel.com>

All errors (new ones prefixed by >>):

>> arch/arm64/kernel/head.S:102:10: error: expected compatible register or logical immediate
    tst x0, #0xf << ID_AA64MMFR2_EL1_LVA_SHIFT
            ^
>> <instantiation>:3:14: error: expected compatible register or logical immediate
    and x3, x3, #(0xf << ID_AA64MMFR2_EL1_LVA_SHIFT)
                ^
   <instantiation>:2:2: note: while in macro instantiation
    offset_ttbr1 x1, x3
    ^
   arch/arm64/kernel/head.S:666:2: note: while in macro instantiation
    load_ttbr1 x1, x1, x3
    ^
   arch/arm64/kernel/head.S:680:14: error: expected compatible register or logical immediate
    and x0, x0, #(0xf << ID_AA64MMFR2_EL1_LVA_SHIFT)
                ^
>> <instantiation>:3:14: error: expected compatible register or logical immediate
    and x2, x2, #(0xf << ID_AA64MMFR2_EL1_LVA_SHIFT)
                ^
   <instantiation>:2:2: note: while in macro instantiation
    offset_ttbr1 x1, x2
    ^
   arch/arm64/kernel/head.S:816:2: note: while in macro instantiation
    load_ttbr1 x1, x1, x2
    ^
--
>> <instantiation>:3:14: error: expected compatible register or logical immediate
    and x2, x2, #(0xf << ID_AA64MMFR2_EL1_LVA_SHIFT)
                ^
   <instantiation>:2:2: note: while in macro instantiation
    offset_ttbr1 x1, x2
    ^
   <instantiation>:6:2: note: while in macro instantiation
    load_ttbr1 x17, x1, x2
    ^
   arch/arm64/kernel/relocate_kernel.S:55:2: note: while in macro instantiation
    break_before_make_ttbr_switch x18, x17, x1, x2
    ^
--
>> <instantiation>:3:14: error: expected compatible register or logical immediate
    and x1, x1, #(0xf << ID_AA64MMFR2_EL1_LVA_SHIFT)
                ^
   <instantiation>:3:2: note: while in macro instantiation
    offset_ttbr1 x3, x1
    ^
   arch/arm64/mm/proc.S:191:2: note: while in macro instantiation
    __idmap_cpu_set_reserved_ttbr1 x1, x3
    ^
>> <instantiation>:3:14: error: expected compatible register or logical immediate
    and x3, x3, #(0xf << ID_AA64MMFR2_EL1_LVA_SHIFT)
                ^
   arch/arm64/mm/proc.S:193:2: note: while in macro instantiation
    offset_ttbr1 x0, x3
    ^


vim +102 arch/arm64/kernel/head.S

9703d9d7f77ce12 Catalin Marinas 2012-03-05   43  
9703d9d7f77ce12 Catalin Marinas 2012-03-05   44  /*
9703d9d7f77ce12 Catalin Marinas 2012-03-05   45   * Kernel startup entry point.
9703d9d7f77ce12 Catalin Marinas 2012-03-05   46   * ---------------------------
9703d9d7f77ce12 Catalin Marinas 2012-03-05   47   *
9703d9d7f77ce12 Catalin Marinas 2012-03-05   48   * The requirements are:
9703d9d7f77ce12 Catalin Marinas 2012-03-05   49   *   MMU = off, D-cache = off, I-cache = on or off,
9703d9d7f77ce12 Catalin Marinas 2012-03-05   50   *   x0 = physical address to the FDT blob.
9703d9d7f77ce12 Catalin Marinas 2012-03-05   51   *
9703d9d7f77ce12 Catalin Marinas 2012-03-05   52   * Note that the callee-saved registers are used for storing variables
9703d9d7f77ce12 Catalin Marinas 2012-03-05   53   * that are useful before the MMU is enabled. The allocations are described
9703d9d7f77ce12 Catalin Marinas 2012-03-05   54   * in the entry routines.
9703d9d7f77ce12 Catalin Marinas 2012-03-05   55   */
9703d9d7f77ce12 Catalin Marinas 2012-03-05   56  	__HEAD
9703d9d7f77ce12 Catalin Marinas 2012-03-05   57  	/*
9703d9d7f77ce12 Catalin Marinas 2012-03-05   58  	 * DO NOT MODIFY. Image header expected by Linux boot-loaders.
9703d9d7f77ce12 Catalin Marinas 2012-03-05   59  	 */
7919385b9fb3cef Ard Biesheuvel  2020-11-17   60  	efi_signature_nop			// special NOP to identity as PE/COFF executable
348a625deef13d7 Ard Biesheuvel  2020-03-26   61  	b	primary_entry			// branch to kernel start, magic
120dc60d0bdbadc Ard Biesheuvel  2020-08-25   62  	.quad	0				// Image load offset from start of RAM, little-endian
6ad1fe5d9077a1a Ard Biesheuvel  2015-12-26   63  	le64sym	_kernel_size_le			// Effective size of kernel image, little-endian
6ad1fe5d9077a1a Ard Biesheuvel  2015-12-26   64  	le64sym	_kernel_flags_le		// Informative flags, little-endian
4370eec05a887b0 Roy Franz       2013-08-15   65  	.quad	0				// reserved
4370eec05a887b0 Roy Franz       2013-08-15   66  	.quad	0				// reserved
4370eec05a887b0 Roy Franz       2013-08-15   67  	.quad	0				// reserved
f56063c51f9fb3d AKASHI Takahiro 2018-11-15   68  	.ascii	ARM64_IMAGE_MAGIC		// Magic number
7919385b9fb3cef Ard Biesheuvel  2020-11-17   69  	.long	.Lpe_header_offset		// Offset to the PE header.
3c7f255039a2ad6 Mark Salter     2014-04-15   70  
b5f4a214b802a72 Ard Biesheuvel  2017-03-23   71  	__EFI_PE_HEADER
9703d9d7f77ce12 Catalin Marinas 2012-03-05   72  
546c8c44f092b2f Ard Biesheuvel  2016-03-30   73  	__INIT
546c8c44f092b2f Ard Biesheuvel  2016-03-30   74  
a9be2ee09385387 Ard Biesheuvel  2016-08-31   75  	/*
a9be2ee09385387 Ard Biesheuvel  2016-08-31   76  	 * The following callee saved general purpose registers are used on the
a9be2ee09385387 Ard Biesheuvel  2016-08-31   77  	 * primary lowlevel boot path:
a9be2ee09385387 Ard Biesheuvel  2016-08-31   78  	 *
a9be2ee09385387 Ard Biesheuvel  2016-08-31   79  	 *  Register   Scope                      Purpose
005e12676af09a3 Ard Biesheuvel  2022-06-24   80  	 *  x20        primary_entry() .. __primary_switch()    CPU boot mode
348a625deef13d7 Ard Biesheuvel  2020-03-26   81  	 *  x21        primary_entry() .. start_kernel()        FDT pointer passed at boot in x0
f70b3a23324a2d3 Ard Biesheuvel  2022-06-24   82  	 *  x22        create_idmap() .. start_kernel()         ID map VA of the DT blob
348a625deef13d7 Ard Biesheuvel  2020-03-26   83  	 *  x23        primary_entry() .. start_kernel()        physical misalignment/KASLR offset
aacd149b62382c6 Ard Biesheuvel  2022-06-24   84  	 *  x24        __primary_switch()                       linear map KASLR seed
0aaa68532e9da5c Ard Biesheuvel  2022-07-01   85  	 *  x25        primary_entry() .. start_kernel()        supported VA size
c3cee924bd85518 Ard Biesheuvel  2022-06-24   86  	 *  x28        create_idmap()                           callee preserved temp register
a9be2ee09385387 Ard Biesheuvel  2016-08-31   87  	 */
348a625deef13d7 Ard Biesheuvel  2020-03-26   88  SYM_CODE_START(primary_entry)
da9c177de88679c Ard Biesheuvel  2015-03-17   89  	bl	preserve_boot_args
ecbb11ab3ebc027 Mark Rutland    2020-11-13   90  	bl	init_kernel_el			// w0=cpu_boot_mode
005e12676af09a3 Ard Biesheuvel  2022-06-24   91  	mov	x20, x0
e42ade29e3bcb32 Ard Biesheuvel  2022-06-24   92  	bl	create_idmap
e42ade29e3bcb32 Ard Biesheuvel  2022-06-24   93  
9703d9d7f77ce12 Catalin Marinas 2012-03-05   94  	/*
a591ede4cd1cac0 Marc Zyngier    2015-03-18   95  	 * The following calls CPU setup code, see arch/arm64/mm/proc.S for
a591ede4cd1cac0 Marc Zyngier    2015-03-18   96  	 * details.
9703d9d7f77ce12 Catalin Marinas 2012-03-05   97  	 * On return, the CPU will be ready for the MMU to be turned on and
9703d9d7f77ce12 Catalin Marinas 2012-03-05   98  	 * the TCR will have been set.
9703d9d7f77ce12 Catalin Marinas 2012-03-05   99  	 */
0aaa68532e9da5c Ard Biesheuvel  2022-07-01  100  #if VA_BITS > 48
0aaa68532e9da5c Ard Biesheuvel  2022-07-01  101  	mrs_s	x0, SYS_ID_AA64MMFR2_EL1
59a377f81d423c2 Mark Brown      2022-07-28 @102  	tst	x0, #0xf << ID_AA64MMFR2_EL1_LVA_SHIFT
0aaa68532e9da5c Ard Biesheuvel  2022-07-01  103  	mov	x0, #VA_BITS
0aaa68532e9da5c Ard Biesheuvel  2022-07-01  104  	mov	x25, #VA_BITS_MIN
0aaa68532e9da5c Ard Biesheuvel  2022-07-01  105  	csel	x25, x25, x0, eq
0aaa68532e9da5c Ard Biesheuvel  2022-07-01  106  	mov	x0, x25
0aaa68532e9da5c Ard Biesheuvel  2022-07-01  107  #endif
0cd3defe0af4153 Ard Biesheuvel  2016-04-18  108  	bl	__cpu_setup			// initialise processor
3c5e9f238bc475b Ard Biesheuvel  2016-08-31  109  	b	__primary_switch
348a625deef13d7 Ard Biesheuvel  2020-03-26  110  SYM_CODE_END(primary_entry)
9703d9d7f77ce12 Catalin Marinas 2012-03-05  111  

:::::: The code at line 102 was first introduced by commit
:::::: 59a377f81d423c2700911143c8b7a2dbb762d27b arm64/sysreg: Add _EL1 into ID_AA64MMFR2_EL1 definition names

:::::: TO: Mark Brown <broonie@kernel.org>
:::::: CC: Mark Brown <broonie@kernel.org>

-- 
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https://01.org/lkp