From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f49.google.com (mail-pj1-f49.google.com [209.85.216.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BDE87EB for ; Wed, 5 Apr 2023 10:46:42 +0000 (UTC) Received: by mail-pj1-f49.google.com with SMTP id p3-20020a17090a74c300b0023f69bc7a68so36812963pjl.4 for ; Wed, 05 Apr 2023 03:46:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680691602; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc:subject:date:message-id:reply-to; bh=otykqullkWmg0A8KD35JF+HvspAaLoRDA6Fr6QFOB1A=; b=UQ0uumG4XH81lWfK6pVQa6G5b2bhg0H+jTMz7NTZVbIIyh41o0CBkytB6xZpFe/MDh Yffh5qenGWrU9TxMdihhNju6UMyitiMEbH/S8wc2qQG1KulmNjPVmxbe+5lvAhEFomTo UVZm4lhSh/J0/m6bMtf8ttgxYxkKl7fMCt60yIF06Ptxf/mvXyFUkNGGUYB2n0DaTbEg azqFX9oSbODaFFg4PbBU08adA+7I25vr0zw2LIqhUF9vuMMdUc7mKurF6cxQ3IPMwZvq T3aNBPO0bWfwSYeSYziw6ebXlP1MKTFYUr1w/FPVCAfBHvf9/tdCNmCXNug8DyFs3WjS 4MCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680691602; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to; bh=otykqullkWmg0A8KD35JF+HvspAaLoRDA6Fr6QFOB1A=; b=7EcIRPofOjeWOz98P7HKUVVOhlrWC23zVU57kN/Ah9geMWNL6jyvWders3M0F2MJTX vDdvLlCU9LKlnNeDLuH0YLEpBOpD2nem/5uogF0kX1z2JQKeDxRFrqsCkgK4Von/r3zA SChe2ltRav16su/tURNB7olBbPRfIAzLYMYz4y6xaWEi2L2fi5eQoB6E7W2b6dM2pJtb jwl+qRaP5IJWaDALUYA5NXVk/JPrYZuLpxLOdwpT3GUnYswZT60MzdfF6rW3iYxx6YAg V65n4W+7HqeP3vtMgOXb5sudtZdmmP61fVluHkFrBOn6bM7W96WJS3Fs+UV9whqyrEay YP5w== X-Gm-Message-State: AAQBX9d+IxxAHpw8mHsrtiz+AtLTNTohK4x7QkAUK7V4lMNVJOrPbOrL Gd9FPslifjpQvy6dR0g/B0FZxQ== X-Google-Smtp-Source: AKy350bK44iNVZ3LLDOTnB4w4y2fswThth90M15FEkZbqe29HOhrRwzj1s6JWfRQJI6BiNBgiUWAxA== X-Received: by 2002:a17:902:e294:b0:1a1:8edc:c5f8 with SMTP id o20-20020a170902e29400b001a18edcc5f8mr4558701plc.56.1680691601853; Wed, 05 Apr 2023 03:46:41 -0700 (PDT) Received: from sunil-laptop ([106.51.184.50]) by smtp.gmail.com with ESMTPSA id g20-20020a62e314000000b0062b5a55835dsm10319322pfh.213.2023.04.05.03.46.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 03:46:41 -0700 (PDT) Date: Wed, 5 Apr 2023 16:16:28 +0530 From: Sunil V L To: Conor Dooley Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev, Weili Qian , Albert Ou , Herbert Xu , Tom Rix , Jonathan Corbet , Marc Zyngier , Daniel Lezcano , Nick Desaulniers , Mark Gross , Hans de Goede , Zhou Wang , Palmer Dabbelt , Paul Walmsley , "Rafael J . Wysocki" , Nathan Chancellor , Thomas Gleixner , Maximilian Luz , "David S . Miller" , Len Brown Subject: Re: [PATCH V4 23/23] crypto: hisilicon/qm: Workaround to enable build with RISC-V clang Message-ID: References: <20230404182037.863533-1-sunilvl@ventanamicro.com> <20230404182037.863533-24-sunilvl@ventanamicro.com> <20230404-viewpoint-shank-674a8940809a@spud> Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230404-viewpoint-shank-674a8940809a@spud> Hi Conor, On Tue, Apr 04, 2023 at 10:59:41PM +0100, Conor Dooley wrote: > Hey Sunil, > > This one made me scratch my head for a bit.. > > On Tue, Apr 04, 2023 at 11:50:37PM +0530, Sunil V L wrote: > > With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in > > allmodconfig build. The gcc tool chain builds this driver removing the > > inline arm64 assembly code. However, clang for RISC-V tries to build > > the arm64 assembly and below error is seen. > > There's actually nothing RISC-V specific about that behaviour, that's > just how clang works. Quoting Nathan: > "Clang performs semantic analysis (i.e., validates assembly) before > dead code elimination, so IS_ENABLED() is not sufficient for avoiding > that error." > Huh, It never occurred to me that this issue could be known already since I always thought we are hitting this first time since ACPI is enabled only now for RISC-V. Thank you very much!. > > drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm > > "+Q" (*((char __iomem *)fun_base)) > > ^ > > It appears that RISC-V clang is not smart enough to detect > > IS_ENABLED(CONFIG_ARM64) and remove the dead code. > > So I think this statement is just not true, it can remove dead code, but > only after it has done the semantic analysis. > Yes, with more details now, let me update the commit message. > The reason that this has not been seen before, again quoting Nathan, is: > "arm64 and x86_64 both support the Q constraint, we cannot build > LoongArch yet (although it does not have support for Q either so same > boat as RISC-V), and ia64 is dead/unsupported in LLVM. Those are the > only architectures that support ACPI, so I guess that explains why we > have seen no issues aside from RISC-V so far." > > > As a workaround, move this check to preprocessing stage which works > > with the RISC-V clang tool chain. > > I don't think there's much else you can do! > Reviewed-by: Conor Dooley > > Perhaps it is also worth adding: > Link: https://github.com/ClangBuiltLinux/linux/issues/999 > Sure, Thank you very much for digging this! Thanks, Sunil