From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pl1-f180.google.com (mail-pl1-f180.google.com [209.85.214.180]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 88203EC5 for ; Wed, 5 Apr 2023 11:11:25 +0000 (UTC) Received: by mail-pl1-f180.google.com with SMTP id z19so34086530plo.2 for ; Wed, 05 Apr 2023 04:11:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1680693085; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=5pxL1NLKIe4ynxwYg+dKy42GRofGXnJPceoZyaJlGsY=; b=nvs4osDtFN/XDWVyPnDEUElo8Qbrje5CpeBg/PRBc/WdVbgB9ZU0SrUP1hJq2ju3DS z9NmJtkGv0DmufyQvLSFnMKjudXf7+3pdmCuK3uwUnVW7GXp/xRnHkpSKUXlNdTWmB5V DbyxwDh01RVrM8HzDoq6knV0uPtMzz7vvOk2W//B8ywv/geATFJI8BNsXBlXzKRVMhs7 VBRFzcpf5O9Tok5o0AYAwQVtUKRyzD5YIjNP/3kZCxSTycUIXisvyUc5EceMPZM8cuwe Meuv2kYW8x+xr8lpCGba+wjBDn/5Q9hhsYYVTFEA4wW4bkE0HV6kcujI83/l7uALfWQI W7cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; t=1680693085; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=5pxL1NLKIe4ynxwYg+dKy42GRofGXnJPceoZyaJlGsY=; b=Mh8xeVFwmlmeWeVbsTJIs1ZFyf1orBhu/AmQiApjL/XGDFY758dRYtDX/ulMwqTf2S 5Yn2yAMEv9SRE13SMs/oW+ei1qJOGmb2cusR6P5NNbT/7sYor1rIhgvQAdXuA9CDlg+p 2vGlQ3718Qlgy/ASudfPUcUBzJSsNkRU0e1oB2gQ/Krxx5uFlbsdZcly/WFwYIue1QcU 4RUMhaVomYYdP6EDoCZHfUBsZ61LxiBoQ+5ywCZ7aML+RN6s+k4HWuPH4qMxKrXO1yab 1HUYuz/0LArikMT8pyoD4vz86ORnfNttkwtyf3xC0PdFCNkChZgAobE2gJJyMGmnQI5R jw9A== X-Gm-Message-State: AAQBX9e54WX8H+x/0sHnUdCGRR62s2jf5Czx/yfeyux+OetdDt34Njyl 3rqRP7yZvxAyuAHwUinonL++mHXTvzV4Kb1bU98= X-Google-Smtp-Source: AKy350YYKcA8GasuUJIRqwG4r5R+Rypm/Vk1KsMv+WRX/0RgSaLSzcfBQVqYKrxKXrfWFx4e0DEqbw== X-Received: by 2002:a05:6a20:8347:b0:cd:1709:8d57 with SMTP id z7-20020a056a20834700b000cd17098d57mr4852595pzc.1.1680693085020; Wed, 05 Apr 2023 04:11:25 -0700 (PDT) Received: from sunil-laptop ([106.51.184.50]) by smtp.gmail.com with ESMTPSA id h18-20020a635752000000b0050301745a5dsm8963209pgm.50.2023.04.05.04.11.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Apr 2023 04:11:24 -0700 (PDT) Date: Wed, 5 Apr 2023 16:41:13 +0530 From: Sunil V L To: Maximilian Luz Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev, Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , Marc Zyngier , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , "Rafael J . Wysocki" , "David S . Miller" Subject: Re: [PATCH V4 22/23] platform/surface: Disable for RISC-V Message-ID: References: <20230404182037.863533-1-sunilvl@ventanamicro.com> <20230404182037.863533-23-sunilvl@ventanamicro.com> <0c433e15-640e-280f-fcb0-a8fe081d1bcc@gmail.com> Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <0c433e15-640e-280f-fcb0-a8fe081d1bcc@gmail.com> On Wed, Apr 05, 2023 at 11:33:00AM +0200, Maximilian Luz wrote: > On 4/4/23 20:20, Sunil V L wrote: > > With CONFIG_ACPI enabled for RISC-V, this driver gets enabled > > in allmodconfig build. However, RISC-V doesn't support sub-word > > atomics which is used by this driver. Due to this, the build fails > > with below error. > > > > In function ‘ssh_seq_next’, > > inlined from ‘ssam_request_write_data’ at drivers/platform/surface/aggregator/controller.c:1483:8: > > ././include/linux/compiler_types.h:399:45: error: call to ‘__compiletime_assert_335’ declared with attribute error: BUILD_BUG failed > > 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > > | ^ > > ./include/linux/compiler.h:78:45: note: in definition of macro ‘unlikely’ > > 78 | # define unlikely(x) __builtin_expect(!!(x), 0) > > | ^ > > ././include/linux/compiler_types.h:387:9: note: in expansion of macro ‘__compiletime_assert’ > > 387 | __compiletime_assert(condition, msg, prefix, suffix) > > | ^~~~~~~~~~~~~~~~~~~~ > > ././include/linux/compiler_types.h:399:9: note: in expansion of macro ‘_compiletime_assert’ > > 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) > > | ^~~~~~~~~~~~~~~~~~~ > > ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’ > > 39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) > > | ^~~~~~~~~~~~~~~~~~ > > ./include/linux/build_bug.h:59:21: note: in expansion of macro ‘BUILD_BUG_ON_MSG’ > > 59 | #define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") > > | ^~~~~~~~~~~~~~~~ > > ./arch/riscv/include/asm/cmpxchg.h:335:17: note: in expansion of macro ‘BUILD_BUG’ > > 335 | BUILD_BUG(); \ > > | ^~~~~~~~~ > > ./arch/riscv/include/asm/cmpxchg.h:344:30: note: in expansion of macro ‘__cmpxchg’ > > 344 | (__typeof__(*(ptr))) __cmpxchg((ptr), \ > > | ^~~~~~~~~ > > ./include/linux/atomic/atomic-instrumented.h:1916:9: note: in expansion of macro ‘arch_cmpxchg’ > > 1916 | arch_cmpxchg(__ai_ptr, __VA_ARGS__); \ > > | ^~~~~~~~~~~~ > > drivers/platform/surface/aggregator/controller.c:61:32: note: in expansion of macro ‘cmpxchg’ > > 61 | while (unlikely((ret = cmpxchg(&c->value, old, new)) != old)) { > > | ^~~~~~~ > > > > So, disable this driver for RISC-V even when ACPI is enabled for now. > > CONFIG_SURFACE_PLATFORMS should be enabled for ARM64 || X86 || COMPILE_TEST only, > so I guess the issue only happens when compiling with the latter enabled? > > I'm not aware of any current plans of MS to release RISC-V-based Surface > devices, so you could maybe also just explicitly disable CONFIG_SURFACE_PLATFORMS. > In any case, I don't see any issues with disabling the whole platform/surface > or only individual drivers for RISC-V, so for either solution: > > Acked-by: Maximilian Luz > Hi Maximilian, Thanks!. Yes, COMPILE_TEST gets enabled for allmodconfig builds. Since the whole intention of COMPILE_TEST appears to be able to compile-test drivers on a platform than they are supposed to be used, I think it is better not to skip whole set of drivers but only that which can not build. So, I prefer to keep this change as is. Thanks, Sunil