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Fri, 25 Jul 2025 07:16:19 -0700 (PDT) Date: Fri, 25 Jul 2025 07:16:15 -0700 From: Deepak Gupta To: Heinrich Schuchardt Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kbuild@vger.kernel.org, linux-mm@kvack.org, llvm@lists.linux.dev, rick.p.edgecombe@intel.com, broonie@kernel.org, cleger@rivosinc.com, samitolvanen@google.com, apatel@ventanamicro.com, ajones@ventanamicro.com, conor.dooley@microchip.com, charlie@rivosinc.com, samuel.holland@sifive.com, bjorn@rivosinc.com, fweimer@redhat.com, jeffreyalaw@gmail.com, andrew@sifive.com, ved@rivosinc.com, Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Masahiro Yamada , Nathan Chancellor , Nicolas Schier , Andrew Morton , David Hildenbrand , Lorenzo Stoakes , "Liam R. Howlett" , Vlastimil Babka , Mike Rapoport , Suren Baghdasaryan , Michal Hocko , Nick Desaulniers , Bill Wendling , Monk Chiang , Kito Cheng , Justin Stitt Subject: Re: [PATCH 02/11] riscv: update asm call site in `call_on_irq_stack` to setup correct label Message-ID: References: <20250724-riscv_kcfi-v1-0-04b8fa44c98c@rivosinc.com> <20250724-riscv_kcfi-v1-2-04b8fa44c98c@rivosinc.com> <4ad699fc-a89d-4740-bdec-ecb9a2134c90@canonical.com> Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <4ad699fc-a89d-4740-bdec-ecb9a2134c90@canonical.com> On Fri, Jul 25, 2025 at 08:23:44AM +0200, Heinrich Schuchardt wrote: >On 25.07.25 01:36, Deepak Gupta wrote: >>Call sites written in asm performing indirect call, they need to setup >>label register (t2/x7) with correct label. >> >>Currently first kernel was compiled with `-save-temps` option and >>normalized function signature string is captured and then placed at the >>asm callsite. >> >>TODO: to write a macro wrapper with toolchain support. >> >>Signed-off-by: Deepak Gupta >>--- >> arch/riscv/kernel/entry.S | 1 + >> 1 file changed, 1 insertion(+) >> >>diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S >>index 2660faf52232..598e17e800ae 100644 >>--- a/arch/riscv/kernel/entry.S >>+++ b/arch/riscv/kernel/entry.S >>@@ -389,6 +389,7 @@ SYM_FUNC_START(call_on_irq_stack) >> load_per_cpu t0, irq_stack_ptr, t1 >> li t1, IRQ_STACK_SIZE >> add sp, t0, t1 >>+ lui t2, %lpad_hash("FvP7pt_regsE") > >In patch 1 you use lpad 0 due to missing tool support for signature hashing. > >Wouldn't it be preferable to have a first patch series introducing >landing pad support with lpad 0 and once tool support for signature >hashing has landed create a second patch series using tags? > >Such a first patch series would not have to be an RFC but might be >merged soon. It's mostly about security guarantees. Coarser grained cfi (only landing pad) has been proved many times not that effective. Kernel is a monolithic piece of code. If there is a good chance of adoption anywhere for labeled landing pads, its kernel. If it becomes a long pole, it's a possible direction to go back to unlabeled landing pad. > >Best regards > >Heinrich > >> jalr a1 >> /* Switch back to the thread shadow call stack */ >> >