From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4F3AC1840 for ; Thu, 21 Apr 2022 01:57:00 +0000 (UTC) X-UUID: 762cc08cd94b4c178222349d9c51143f-20220421 X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.4,REQID:bf634d14-d05d-48f9-97af-3c785fa8e38b,OB:0,LO B:0,IP:0,URL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:faefae9,CLOUDID:976993ef-06b0-4305-bfbf-554bfc9d151a,C OID:IGNORED,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,File:nil,QS:0,BEC:nil X-UUID: 762cc08cd94b4c178222349d9c51143f-20220421 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1879615872; Thu, 21 Apr 2022 09:56:55 +0800 Received: from mtkcas10.mediatek.inc (172.21.101.39) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 21 Apr 2022 09:56:53 +0800 Received: from mtksdccf07 (172.21.84.99) by mtkcas10.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Thu, 21 Apr 2022 09:56:53 +0800 Message-ID: Subject: Re: [PATCH v17 07/21] soc: mediatek: mmsys: modify reset controller for MT8195 vdosys1 From: Rex-BC Chen To: Nancy.Lin , Rob Herring , Matthias Brugger , Chun-Kuang Hu , Philipp Zabel , "wim@linux-watchdog.org" , "AngeloGioacchino Del Regno" , "linux@roeck-us.net" CC: David Airlie , Daniel Vetter , "Nathan Chancellor" , Nick Desaulniers , Jason-JH Lin =?UTF-8?Q?=28=E6=9E=97=E7=9D=BF=E7=A5=A5=29?= , Yongqiang Niu =?UTF-8?Q?=28=E7=89=9B=E6=B0=B8=E5=BC=BA=29?= , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-mediatek@lists.infradead.org" , "dri-devel@lists.freedesktop.org" , "llvm@lists.linux.dev" , Singo Chang =?UTF-8?Q?=28=E5=BC=B5=E8=88=88=E5=9C=8B=29?= , srv_heupstream , Project_Global_Chrome_Upstream_Group Date: Thu, 21 Apr 2022 09:56:53 +0800 In-Reply-To: <20220416020749.29010-8-nancy.lin@mediatek.com> References: <20220416020749.29010-1-nancy.lin@mediatek.com> <20220416020749.29010-8-nancy.lin@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.28.5-0ubuntu0.18.04.2 Precedence: bulk X-Mailing-List: llvm@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N On Sat, 2022-04-16 at 10:07 +0800, Nancy.Lin wrote: > MT8195 vdosys1 has more than 32 reset bits and a different reset base > than other chips. Modify mmsys for support 64 bit and different reset > base. > > Signed-off-by: Nancy.Lin > Reviewed-by: AngeloGioacchino Del Regno < > angelogioacchino.delregno@collabora.com> > --- Reviewed-by: Rex-BC Chen