[PATCH v4] Subject: PCI: Enable io space 1k granularity for intel cpu root port

Zhou Shengqing
2024-07-02T03:57:10Z

This patch add 1k granularity for intel root port bridge. Intel latest
server CPU support 1K granularity, And there is an BIOS setup item named
"EN1K", but linux doesn't support it. if an IIO has 5 IOU (SPR has 5 IOUs)
all are bifurcated 2x8.In a 2P server system,There are 20 P2P bridges
present. if keep 4K granularity allocation,it need 20*4=80k io space,
exceeding 64k. I test it in a 16*nvidia 4090s system under intel eaglestrem
platform. There are six 4090s that cannot be allocated I/O resources.
So I applied this patch. And I found a similar implementation in quirks.c,
but it only targets the Intel P64H2 platform.

Signed-off-by: Zhou Shengqing <zhoushengqing@ttyinfo.com>
---
drivers/pci/quirks.c | 30 ++++++++++++++++++++++++++++++
1 file changed, 30 insertions(+)

diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 568410e64ce6..f30083d51e15 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -2562,6 +2562,36 @@ static void quirk_p64h2_1k_io(struct pci_dev *dev)
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);

+/* Enable 1k I/O space granularity on the intel root port */
+static void quirk_intel_rootport_1k_io(struct pci_dev *dev)
+{
+ struct pci_dev *d = NULL;
+ u16 en1k = 0;
+ struct pci_dev *root_port = pcie_find_root_port(dev);
+
+ if (!root_port)
+ return;
+
+ /*
+ * Per intel sever CPU EDS vol2(register) spec,
+ * Intel Memory Map/Intel VT-d configuration space,
+ * IIO MISC Control (IIOMISCCTRL_1_5_0_CFG) — Offset 1C0h
+ * bit 2.
+ * Enable 1K (EN1K):
+ * This bit when set, enables 1K granularity for I/O space decode
+ * in each of the virtual P2P bridges
+ * corresponding to root ports, and DMI ports.
+ */
+ while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, 0x09a2, d))) {
+ pci_read_config_word(d, 0x1c0, &en1k);
+ if (en1k & 0x4) {
+ pci_info(d, "INTEL: System should support 1k io window\n");
+ dev->io_window_1k = 1;
+ }
+ }
+}
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, quirk_intel_rootport_1k_io);
+
/*
* Under some circumstances, AER is not linked with extended capabilities.
* Force it to be linked by setting the corresponding control bit in the
--
2.39.2