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From: George Guo <dongtai.guo@linux.dev>
To: hengqi.chen@gmail.com
Cc: chenhuacai@kernel.org, dongtai.guo@linux.dev,
	guodongtai@kylinos.cn, kernel@xen0n.name,
	lianyangyang@kylinos.cn, linux-kernel@vger.kernel.org,
	loongarch@lists.linux.dev, r@hev.cc, xry111@xry111.site
Subject: [PATCH loongarch-next 2/4] LoongArch: Add 128-bit atomic cmpxchg support
Date: Mon, 29 Dec 2025 14:34:06 +0800	[thread overview]
Message-ID: <20251229063408.34340-3-dongtai.guo@linux.dev> (raw)
In-Reply-To: <20251229063408.34340-1-dongtai.guo@linux.dev>

From: George Guo <guodongtai@kylinos.cn>

Implement 128-bit atomic compare-and-exchange using LoongArch's
LL.D/SC.Q instructions.

At the same time, fix BPF scheduler test failures (scx_central scx_qmap)
caused by kmalloc_nolock_noprof returning NULL due to missing
128-bit atomics. The NULL returns led to -ENOMEM errors during
scheduler initialization, causing test cases to fail.

Verified by testing with the scx_qmap scheduler (located in
tools/sched_ext/). Building with `make` and running
./tools/sched_ext/build/bin/scx_qmap.

Signed-off-by: George Guo <guodongtai@kylinos.cn>
---
 arch/loongarch/include/asm/cmpxchg.h | 47 ++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

diff --git a/arch/loongarch/include/asm/cmpxchg.h b/arch/loongarch/include/asm/cmpxchg.h
index 0494c2ab553e..61ce6a0889f0 100644
--- a/arch/loongarch/include/asm/cmpxchg.h
+++ b/arch/loongarch/include/asm/cmpxchg.h
@@ -137,6 +137,44 @@ __arch_xchg(volatile void *ptr, unsigned long x, int size)
 	__ret;								\
 })
 
+union __u128_halves {
+	u128 full;
+	struct {
+		u64 low;
+		u64 high;
+	};
+};
+
+#define __cmpxchg128_asm(ptr, old, new)					\
+({									\
+	union __u128_halves __old, __new, __ret;			\
+	volatile u64 *__ptr = (volatile u64 *)(ptr);			\
+									\
+	__old.full = (old);                                             \
+	__new.full = (new);						\
+									\
+	__asm__ __volatile__(						\
+	"1:   ll.d    %0, %3		# 128-bit cmpxchg low	\n"	\
+	__WEAK_LLSC_MB							\
+	"     ld.d    %1, %4		# 128-bit cmpxchg high	\n"	\
+	"     bne     %0, %z5, 2f				\n"	\
+	"     bne     %1, %z6, 2f				\n"	\
+	"     move    $t0, %z7					\n"	\
+	"     move    $t1, %z8					\n"	\
+	"     sc.q    $t0, $t1, %2				\n"	\
+	"     beqz    $t0, 1b					\n"	\
+	"2:							\n"	\
+	__WEAK_LLSC_MB							\
+	: "=&r" (__ret.low), "=&r" (__ret.high)				\
+	: "r" (__ptr),							\
+	  "ZC" (__ptr[0]), "m" (__ptr[1]),				\
+	  "Jr" (__old.low), "Jr" (__old.high),				\
+	  "Jr" (__new.low), "Jr" (__new.high)				\
+	: "t0", "t1", "memory");					\
+									\
+	__ret.full;							\
+})
+
 static inline unsigned int __cmpxchg_small(volatile void *ptr, unsigned int old,
 					   unsigned int new, unsigned int size)
 {
@@ -224,6 +262,15 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, unsigned int
 	__res;								\
 })
 
+/* cmpxchg128 */
+#define system_has_cmpxchg128()		1
+
+#define arch_cmpxchg128(ptr, o, n)					\
+({									\
+	BUILD_BUG_ON(sizeof(*(ptr)) != 16);				\
+	__cmpxchg128_asm(ptr, o, n);					\
+})
+
 #ifdef CONFIG_64BIT
 #define arch_cmpxchg64_local(ptr, o, n)					\
   ({									\
-- 
2.49.0


  parent reply	other threads:[~2025-12-29  6:34 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-12-15  8:11 [PATCH v6 0/4] LoongArch: Add 128-bit atomic cmpxchg support (v5) George Guo
2025-12-15  8:11 ` [PATCH v6 1/4] LoongArch: Add SCQ support detection George Guo
2025-12-15  8:11 ` [PATCH v6 2/4] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-15  8:11 ` [PATCH v6 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg George Guo
2025-12-20 13:41 ` [PATCH v6 0/4] LoongArch: Add 128-bit atomic cmpxchg support (v5) Hengqi Chen
2025-12-29  6:34   ` [PATCH loongarch-next 0/4] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-29  6:34     ` [PATCH loongarch-next 1/4] LoongArch: Add SCQ support detection George Guo
2025-12-29  6:34     ` George Guo [this message]
2025-12-29  6:34     ` [PATCH loongarch-next 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg George Guo
2025-12-29  6:34     ` [PATCH loongarch-next 4/4] LoongArch: Enable 128-bit atomics cmpxchg support George Guo
2025-12-29 14:21     ` [PATCH loongarch-next 0/4] LoongArch: Add 128-bit atomic " Hengqi Chen
2025-12-30  1:34       ` [PATCH v7 " George Guo
2025-12-30  1:34         ` [PATCH v7 loongarch-next 1/4] LoongArch: Add SCQ support detection George Guo
2025-12-30 12:05           ` Hengqi Chen
2025-12-30 12:07           ` Hengqi Chen
2025-12-30  1:34         ` [PATCH v7 loongarch-next 2/4] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-30 12:17           ` Hengqi Chen
2025-12-30  1:34         ` [PATCH v7 loongarch-next 3/4] LoongArch: Use spinlock to emulate 128-bit cmpxchg George Guo
2025-12-30  1:34         ` [PATCH v7 loongarch-next 4/4] LoongArch: Enable 128-bit atomics cmpxchg support George Guo
2025-12-30 12:19           ` Hengqi Chen
2025-12-30 12:04         ` [PATCH v7 loongarch-next 0/4] LoongArch: Add 128-bit atomic " Hengqi Chen
2025-12-31  3:45           ` [PATCH v8 loongarch-next 0/3] " George Guo
2025-12-31  3:45             ` [PATCH v8 loongarch-next 1/3] LoongArch: Add SCQ support detection George Guo
2025-12-31  9:51               ` Hengqi Chen
2025-12-31  3:45             ` [PATCH v8 loongarch-next 2/3] LoongArch: Add 128-bit atomic cmpxchg support George Guo
2025-12-31  9:53               ` Hengqi Chen
2025-12-31  3:45             ` [PATCH v8 loongarch-next 3/3] LoongArch: Enable 128-bit atomics " George Guo
2025-12-31  9:52               ` Hengqi Chen
2025-12-31  9:56             ` [PATCH v8 loongarch-next 0/3] LoongArch: Add 128-bit atomic " Huacai Chen
2025-12-20 13:55 ` [PATCH v6 0/4] LoongArch: Add 128-bit atomic cmpxchg support (v5) Hengqi Chen

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