[PATCH v2 1/2] LoongArch: Add flush_icache_all()/local_flush_icache_all()

[PATCH v2 1/2] LoongArch: Add flush_icache_all()/local_flush_icache_all()

[Youling Tang]

From: Youling Tang <tangyouling@kylinos.cn>

LoongArch maintains ICache/DCache coherency by hardware,
we just need "ibar 0" to avoid instruction hazard here.

Signed-off-by: Youling Tang <tangyouling@kylinos.cn>
---
 arch/loongarch/include/asm/cacheflush.h | 16 +++++++++++++++-
 arch/loongarch/mm/cache.c               | 10 ----------
 2 files changed, 15 insertions(+), 11 deletions(-)

diff --git a/arch/loongarch/include/asm/cacheflush.h b/arch/loongarch/include/asm/cacheflush.h
index f8754d08a31a..95416e788d2a 100644
--- a/arch/loongarch/include/asm/cacheflush.h
+++ b/arch/loongarch/include/asm/cacheflush.h
@@ -32,8 +32,22 @@ static inline unsigned int cpu_last_level_cache_line_size(void)
 }
 
 asmlinkage void __flush_cache_all(void);
-void local_flush_icache_range(unsigned long start, unsigned long end);
 
+/*
+ * LoongArch maintains ICache/DCache coherency by hardware,
+ * we just need "ibar" to avoid instruction hazard here.
+ */
+static inline void local_flush_icache_all(void)
+{
+	asm volatile ("ibar\t0\n"::);;
+}
+
+static inline void local_flush_icache_range(unsigned long start, unsigned long end)
+{
+	asm volatile ("ibar\t0\n"::);;
+}
+
+#define flush_icache_all	local_flush_icache_all
 #define flush_icache_range	local_flush_icache_range
 #define flush_icache_user_range	local_flush_icache_range
 
diff --git a/arch/loongarch/mm/cache.c b/arch/loongarch/mm/cache.c
index 496916845ff7..06dc570eb429 100644
--- a/arch/loongarch/mm/cache.c
+++ b/arch/loongarch/mm/cache.c
@@ -31,16 +31,6 @@ void cache_error_setup(void)
 	set_merr_handler(0x0, &except_vec_cex, 0x80);
 }
 
-/*
- * LoongArch maintains ICache/DCache coherency by hardware,
- * we just need "ibar" to avoid instruction hazard here.
- */
-void local_flush_icache_range(unsigned long start, unsigned long end)
-{
-	asm volatile ("\tibar 0\n"::);
-}
-EXPORT_SYMBOL(local_flush_icache_range);
-
 static void flush_cache_leaf(unsigned int leaf)
 {
 	int i, j, nr_nodes;
-- 
2.43.0

[PATCH v2 2/2] LoongArch: Batch icache maintenance for jump_label

[Youling Tang]

From: Youling Tang <tangyouling@kylinos.cn>

Switch to the batched version of the jump label update functions so
instruction cache maintenance is deferred until the end of the update.

Signed-off-by: Youling Tang <tangyouling@kylinos.cn>
---
 arch/loongarch/include/asm/jump_label.h |  1 +
 arch/loongarch/kernel/inst.c            |  6 +++---
 arch/loongarch/kernel/jump_label.c      | 13 +++++++++++--
 3 files changed, 15 insertions(+), 5 deletions(-)

diff --git a/arch/loongarch/include/asm/jump_label.h b/arch/loongarch/include/asm/jump_label.h
index dcaecf69ea5a..ceb3dfa66188 100644
--- a/arch/loongarch/include/asm/jump_label.h
+++ b/arch/loongarch/include/asm/jump_label.h
@@ -13,6 +13,7 @@
 #include <linux/stringify.h>
 #include <asm/asm.h>
 
+#define HAVE_JUMP_LABEL_BATCH
 #define JUMP_LABEL_NOP_SIZE	4
 
 #ifdef CONFIG_32BIT
diff --git a/arch/loongarch/kernel/inst.c b/arch/loongarch/kernel/inst.c
index 1a728082944c..0b9228b7c13a 100644
--- a/arch/loongarch/kernel/inst.c
+++ b/arch/loongarch/kernel/inst.c
@@ -209,6 +209,9 @@ int larch_insn_write(void *addr, u32 insn)
 	int ret;
 	unsigned long flags = 0;
 
+	if ((unsigned long)addr & 3)
+		return -EINVAL;
+
 	raw_spin_lock_irqsave(&patch_lock, flags);
 	ret = copy_to_kernel_nofault(addr, &insn, LOONGARCH_INSN_SIZE);
 	raw_spin_unlock_irqrestore(&patch_lock, flags);
@@ -221,9 +224,6 @@ int larch_insn_patch_text(void *addr, u32 insn)
 	int ret;
 	u32 *tp = addr;
 
-	if ((unsigned long)tp & 3)
-		return -EINVAL;
-
 	ret = larch_insn_write(tp, insn);
 	if (!ret)
 		flush_icache_range((unsigned long)tp,
diff --git a/arch/loongarch/kernel/jump_label.c b/arch/loongarch/kernel/jump_label.c
index 31891214b767..f5a394bdb5f3 100644
--- a/arch/loongarch/kernel/jump_label.c
+++ b/arch/loongarch/kernel/jump_label.c
@@ -6,9 +6,11 @@
  */
 #include <linux/kernel.h>
 #include <linux/jump_label.h>
+#include <asm/cacheflush.h>
 #include <asm/inst.h>
 
-void arch_jump_label_transform(struct jump_entry *entry, enum jump_label_type type)
+bool arch_jump_label_transform_queue(struct jump_entry *entry,
+				     enum jump_label_type type)
 {
 	u32 insn;
 	void *addr = (void *)jump_entry_code(entry);
@@ -18,5 +20,12 @@ void arch_jump_label_transform(struct jump_entry *entry, enum jump_label_type ty
 	else
 		insn = larch_insn_gen_nop();
 
-	larch_insn_patch_text(addr, insn);
+	larch_insn_write(addr, insn);
+
+	return true;
+}
+
+void arch_jump_label_transform_apply(void)
+{
+	flush_icache_all();
 }
-- 
2.43.0

Re: [PATCH v2 2/2] LoongArch: Batch icache maintenance for jump_label

[Huacai Chen]

Applied, thanks.


Huacai

On Sun, Apr 5, 2026 at 10:13 AM Youling Tang <youling.tang@linux.dev> wrote:
>
> From: Youling Tang <tangyouling@kylinos.cn>
>
> Switch to the batched version of the jump label update functions so
> instruction cache maintenance is deferred until the end of the update.
>
> Signed-off-by: Youling Tang <tangyouling@kylinos.cn>
> ---
>  arch/loongarch/include/asm/jump_label.h |  1 +
>  arch/loongarch/kernel/inst.c            |  6 +++---
>  arch/loongarch/kernel/jump_label.c      | 13 +++++++++++--
>  3 files changed, 15 insertions(+), 5 deletions(-)
>
> diff --git a/arch/loongarch/include/asm/jump_label.h b/arch/loongarch/include/asm/jump_label.h
> index dcaecf69ea5a..ceb3dfa66188 100644
> --- a/arch/loongarch/include/asm/jump_label.h
> +++ b/arch/loongarch/include/asm/jump_label.h
> @@ -13,6 +13,7 @@
>  #include <linux/stringify.h>
>  #include <asm/asm.h>
>
> +#define HAVE_JUMP_LABEL_BATCH
>  #define JUMP_LABEL_NOP_SIZE    4
>
>  #ifdef CONFIG_32BIT
> diff --git a/arch/loongarch/kernel/inst.c b/arch/loongarch/kernel/inst.c
> index 1a728082944c..0b9228b7c13a 100644
> --- a/arch/loongarch/kernel/inst.c
> +++ b/arch/loongarch/kernel/inst.c
> @@ -209,6 +209,9 @@ int larch_insn_write(void *addr, u32 insn)
>         int ret;
>         unsigned long flags = 0;
>
> +       if ((unsigned long)addr & 3)
> +               return -EINVAL;
> +
>         raw_spin_lock_irqsave(&patch_lock, flags);
>         ret = copy_to_kernel_nofault(addr, &insn, LOONGARCH_INSN_SIZE);
>         raw_spin_unlock_irqrestore(&patch_lock, flags);
> @@ -221,9 +224,6 @@ int larch_insn_patch_text(void *addr, u32 insn)
>         int ret;
>         u32 *tp = addr;
>
> -       if ((unsigned long)tp & 3)
> -               return -EINVAL;
> -
>         ret = larch_insn_write(tp, insn);
>         if (!ret)
>                 flush_icache_range((unsigned long)tp,
> diff --git a/arch/loongarch/kernel/jump_label.c b/arch/loongarch/kernel/jump_label.c
> index 31891214b767..f5a394bdb5f3 100644
> --- a/arch/loongarch/kernel/jump_label.c
> +++ b/arch/loongarch/kernel/jump_label.c
> @@ -6,9 +6,11 @@
>   */
>  #include <linux/kernel.h>
>  #include <linux/jump_label.h>
> +#include <asm/cacheflush.h>
>  #include <asm/inst.h>
>
> -void arch_jump_label_transform(struct jump_entry *entry, enum jump_label_type type)
> +bool arch_jump_label_transform_queue(struct jump_entry *entry,
> +                                    enum jump_label_type type)
>  {
>         u32 insn;
>         void *addr = (void *)jump_entry_code(entry);
> @@ -18,5 +20,12 @@ void arch_jump_label_transform(struct jump_entry *entry, enum jump_label_type ty
>         else
>                 insn = larch_insn_gen_nop();
>
> -       larch_insn_patch_text(addr, insn);
> +       larch_insn_write(addr, insn);
> +
> +       return true;
> +}
> +
> +void arch_jump_label_transform_apply(void)
> +{
> +       flush_icache_all();
>  }
> --
> 2.43.0
>