[PATCH v10 0/3] LoongArch: Add Loongson-2K BMC support

[PATCH v10 0/3] LoongArch: Add Loongson-2K BMC support

[Binbin Zhou]

Hi all:

This patch set introduces the Loongson-2K BMC.

It is a PCIe device present on servers similar to the Loongson-3 CPUs.
And it is a multifunctional device (MFD), such as display as a sub-function
of it.

For IPMI, according to the existing design, we use software simulation to
implement the KCS interface registers: Stauts/Command/Data_Out/Data_In.

Also since both host side and BMC side read and write kcs status, we use
fifo pointer to ensure data consistency.

For the display, based on simpledrm, the resolution is read from a fixed
position in the BMC since the hardware does not support auto-detection
of the resolution. Of course, we will try to support multiple
resolutions later, through a vbios-like approach.

Especially, for the BMC reset function, since the display will be
disconnected when BMC reset, we made a special treatment of re-push.

Based on this, I will present it in four patches:
patch-1: BMC device PCI resource allocation.
patch-2: BMC reset function support
patch-3: IPMI implementation

Thanks.

-------
V10:
Patch (2/3):
 - The PTR_ERR(NULL) is success. It should be "ret = -ENOMEM;".
    - https://lore.kernel.org/all/202508191519.uT5io1jk-lkp@intel.com/

Link to V9:
https://lore.kernel.org/all/cover.1754999365.git.zhoubinbin@loongson.cn/

V9:
Patch (2/3):
 - PCIE -> PCI-E in dev_err();
 - Separate the read from the write;

Link to V8:
https://lore.kernel.org/all/cover.1752548073.git.zhoubinbin@loongson.cn/

V8:
Patch (1/3):
 - Similar to as3711_subdevs, identify elements in ls2k_bmc_cells.

Patch (2/3):
 - Rename variables using usual names, such as `priv` -> `ddata`;
 - Use if statements instead of #ifery;
 - Rewrite the error message to ensure it is easy to understand;
 - ls2k_bmc_pdata_initial(dev, priv); -> ls2k_bmc_pdata_initial(priv);

Link to V7:
https://lore.kernel.org/all/cover.1751617911.git.zhoubinbin@loongson.cn/

V7:
Patch (1/3):
  - Fix build warning by lkp: Add depend on ACPI_GENERIC_GSI
    - https://lore.kernel.org/all/202507021011.sDAHGinj-lkp@intel.com/

Link to V6:
https://lore.kernel.org/all/cover.1750939357.git.zhoubinbin@loongson.cn/

V6:
- Add Acked-by tag from Corey, thanks;
Patch (1/3):
  - Fix build warning by lkp: Add depend on PCI
    - https://lore.kernel.org/all/202506210204.LVZc2VG2-lkp@intel.com/
    - https://lore.kernel.org/all/202506210231.ZWWNhofU-lkp@intel.com/
    - https://lore.kernel.org/all/202506210652.ipUFDU5B-lkp@intel.com/
    - https://lore.kernel.org/all/202506210343.XCHkzorp-lkp@intel.com/

Link to V5:
https://lore.kernel.org/all/cover.1750301674.git.zhoubinbin@loongson.cn/

V5:
Patch (1/3):
 - Rename ls2kbmc-mfd.c to ls2k-bmc-core.c;
 - Rename MFD_LS2K_BMC to MFD_LS2K_BMC_CORE and update its help text.
Patch (3/3):
 - Add an IPMI_LS2K config in the IPMI section that enables the IPMI
   interface and selects MFD_LS2K_BMC_CORE.

Link to V4:
https://lore.kernel.org/all/cover.1749731531.git.zhoubinbin@loongson.cn/

V4:
- Add Reviewed-by tag;
- Change the order of the patches.
Patch (1/3):
  - Fix build warning by lkp: Kconfig tristate -> bool
    - https://lore.kernel.org/all/202505312022.QmFmGE1F-lkp@intel.com/
 - Update commit message;
 - Move MFD_LS2K_BMC after MFD_INTEL_M10_BMC_PMCI in Kconfig and
   Makefile.
Patch (2/3):
  - Remove unnecessary newlines;
  - Rename ls2k_bmc_check_pcie_connected() to
    ls2k_bmc_pcie_is_connected();
  - Update comment message.
Patch (3/3):
  - Remove unnecessary newlines.

Link to V3:
https://lore.kernel.org/all/cover.1748505446.git.zhoubinbin@loongson.cn/

V3:
Patch (1/3):
 - Drop "MFD" in title and comment;
 - Fromatting code;
 - Add clearer comments.
Patch (2/3):
 - Rebase linux-ipmi/next tree;
 - Use readx()/writex() to read and write IPMI data instead of structure
   pointer references;
 - CONFIG_LOONGARCH -> MFD_LS2K_BMC;
 - Drop unused output.
Patch (3/3):
 - Inline the ls2k_bmc_gpio_reset_handler() function to ls2k_bmc_pdata_initial();
 - Add clearer comments.
 - Use proper multi-line commentary as per the Coding Style documentation;
 - Define all magic numbers.

Link to V2:
https://lore.kernel.org/all/cover.1747276047.git.zhoubinbin@loongson.cn/

V2:
- Drop ls2kdrm, use simpledrm instead.
Patch (1/3):
 - Use DEFINE_RES_MEM_NAMED/MFD_CELL_RES simplified code;
 - Add resolution fetching due to replacing the original display
   solution with simpledrm; 
 - Add aperture_remove_conflicting_devices() to avoid efifb
   conflict with simpledrm.
Patch (3/3):
 - This part of the function, moved from the original ls2kdrm to mfd;
 - Use set_console to implement the Re-push display function.

Link to V1:
https://lore.kernel.org/all/cover.1735550269.git.zhoubinbin@loongson.cn/

Binbin Zhou (3):
  mfd: ls2kbmc: Introduce Loongson-2K BMC core driver
  mfd: ls2kbmc: Add Loongson-2K BMC reset function support
  ipmi: Add Loongson-2K BMC support

 MAINTAINERS                      |   7 +
 drivers/char/ipmi/Kconfig        |   7 +
 drivers/char/ipmi/Makefile       |   1 +
 drivers/char/ipmi/ipmi_si.h      |   7 +
 drivers/char/ipmi/ipmi_si_intf.c |   4 +
 drivers/char/ipmi/ipmi_si_ls2k.c | 189 +++++++++++
 drivers/mfd/Kconfig              |  13 +
 drivers/mfd/Makefile             |   2 +
 drivers/mfd/ls2k-bmc-core.c      | 525 +++++++++++++++++++++++++++++++
 9 files changed, 755 insertions(+)
 create mode 100644 drivers/char/ipmi/ipmi_si_ls2k.c
 create mode 100644 drivers/mfd/ls2k-bmc-core.c


base-commit: c0eb742dd61cd6809c480d2c9687d78fce941225
-- 
2.47.3

[PATCH v10 1/3] mfd: ls2kbmc: Introduce Loongson-2K BMC core driver

[Binbin Zhou]

The Loongson-2K Board Management Controller provides an PCIe interface
to the host to access the feature implemented in the BMC.

The BMC is assembled on a server similar to the server machine with
Loongson-3 CPU. It supports multiple sub-devices like DRM and IPMI.

Co-developed-by: Chong Qiao <qiaochong@loongson.cn>
Signed-off-by: Chong Qiao <qiaochong@loongson.cn>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Acked-by: Corey Minyard <corey@minyard.net>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
 MAINTAINERS                 |   6 ++
 drivers/mfd/Kconfig         |  13 +++
 drivers/mfd/Makefile        |   2 +
 drivers/mfd/ls2k-bmc-core.c | 189 ++++++++++++++++++++++++++++++++++++
 4 files changed, 210 insertions(+)
 create mode 100644 drivers/mfd/ls2k-bmc-core.c

diff --git a/MAINTAINERS b/MAINTAINERS
index fe168477caa4..48783add7a8b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14408,6 +14408,12 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml
 F:	drivers/thermal/loongson2_thermal.c
 
+LOONGSON-2K Board Management Controller (BMC) DRIVER
+M:	Binbin Zhou <zhoubinbin@loongson.cn>
+M:	Chong Qiao <qiaochong@loongson.cn>
+S:	Maintained
+F:	drivers/mfd/ls2k-bmc-core.c
+
 LOONGSON EDAC DRIVER
 M:	Zhao Qunqin <zhaoqunqin@loongson.cn>
 L:	linux-edac@vger.kernel.org
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index a403a3daedd5..5c6a7f2e1154 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -2428,6 +2428,19 @@ config MFD_INTEL_M10_BMC_PMCI
 	  additional drivers must be enabled in order to use the functionality
 	  of the device.
 
+config MFD_LS2K_BMC_CORE
+	bool "Loongson-2K Board Management Controller Support"
+	depends on PCI && ACPI_GENERIC_GSI
+	select MFD_CORE
+	help
+	  Say yes here to add support for the Loongson-2K BMC which is a Board
+	  Management Controller connected to the PCIe bus. The device supports
+	  multiple sub-devices like display and IPMI. This driver provides common
+	  support for accessing the devices.
+
+	  The display is enabled by default in the driver, while the IPMI interface
+	  is enabled independently through the IPMI_LS2K option in the IPMI section.
+
 config MFD_QNAP_MCU
 	tristate "QNAP microcontroller unit core driver"
 	depends on SERIAL_DEV_BUS
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index f7bdedd5a66d..a950e670efba 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -286,6 +286,8 @@ obj-$(CONFIG_MFD_INTEL_M10_BMC_CORE)   += intel-m10-bmc-core.o
 obj-$(CONFIG_MFD_INTEL_M10_BMC_SPI)    += intel-m10-bmc-spi.o
 obj-$(CONFIG_MFD_INTEL_M10_BMC_PMCI)   += intel-m10-bmc-pmci.o
 
+obj-$(CONFIG_MFD_LS2K_BMC_CORE)		+= ls2k-bmc-core.o
+
 obj-$(CONFIG_MFD_ATC260X)	+= atc260x-core.o
 obj-$(CONFIG_MFD_ATC260X_I2C)	+= atc260x-i2c.o
 
diff --git a/drivers/mfd/ls2k-bmc-core.c b/drivers/mfd/ls2k-bmc-core.c
new file mode 100644
index 000000000000..39cc481d9ba1
--- /dev/null
+++ b/drivers/mfd/ls2k-bmc-core.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Loongson-2K Board Management Controller (BMC) Core Driver.
+ *
+ * Copyright (C) 2024-2025 Loongson Technology Corporation Limited.
+ *
+ * Authors:
+ *	Chong Qiao <qiaochong@loongson.cn>
+ *	Binbin Zhou <zhoubinbin@loongson.cn>
+ */
+
+#include <linux/aperture.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/mfd/core.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/pci_ids.h>
+#include <linux/platform_data/simplefb.h>
+#include <linux/platform_device.h>
+
+/* LS2K BMC resources */
+#define LS2K_DISPLAY_RES_START		(SZ_16M + SZ_2M)
+#define LS2K_IPMI_RES_SIZE		0x1C
+#define LS2K_IPMI0_RES_START		(SZ_16M + 0xF00000)
+#define LS2K_IPMI1_RES_START		(LS2K_IPMI0_RES_START + LS2K_IPMI_RES_SIZE)
+#define LS2K_IPMI2_RES_START		(LS2K_IPMI1_RES_START + LS2K_IPMI_RES_SIZE)
+#define LS2K_IPMI3_RES_START		(LS2K_IPMI2_RES_START + LS2K_IPMI_RES_SIZE)
+#define LS2K_IPMI4_RES_START		(LS2K_IPMI3_RES_START + LS2K_IPMI_RES_SIZE)
+
+enum {
+	LS2K_BMC_DISPLAY,
+	LS2K_BMC_IPMI0,
+	LS2K_BMC_IPMI1,
+	LS2K_BMC_IPMI2,
+	LS2K_BMC_IPMI3,
+	LS2K_BMC_IPMI4,
+};
+
+static struct resource ls2k_display_resources[] = {
+	DEFINE_RES_MEM_NAMED(LS2K_DISPLAY_RES_START, SZ_4M, "simpledrm-res"),
+};
+
+static struct resource ls2k_ipmi0_resources[] = {
+	DEFINE_RES_MEM_NAMED(LS2K_IPMI0_RES_START, LS2K_IPMI_RES_SIZE, "ipmi0-res"),
+};
+
+static struct resource ls2k_ipmi1_resources[] = {
+	DEFINE_RES_MEM_NAMED(LS2K_IPMI1_RES_START, LS2K_IPMI_RES_SIZE, "ipmi1-res"),
+};
+
+static struct resource ls2k_ipmi2_resources[] = {
+	DEFINE_RES_MEM_NAMED(LS2K_IPMI2_RES_START, LS2K_IPMI_RES_SIZE, "ipmi2-res"),
+};
+
+static struct resource ls2k_ipmi3_resources[] = {
+	DEFINE_RES_MEM_NAMED(LS2K_IPMI3_RES_START, LS2K_IPMI_RES_SIZE, "ipmi3-res"),
+};
+
+static struct resource ls2k_ipmi4_resources[] = {
+	DEFINE_RES_MEM_NAMED(LS2K_IPMI4_RES_START, LS2K_IPMI_RES_SIZE, "ipmi4-res"),
+};
+
+static struct mfd_cell ls2k_bmc_cells[] = {
+	[LS2K_BMC_DISPLAY] = {
+		.name = "simple-framebuffer",
+		.num_resources = ARRAY_SIZE(ls2k_display_resources),
+		.resources = ls2k_display_resources
+	},
+	[LS2K_BMC_IPMI0] = {
+		.name = "ls2k-ipmi-si",
+		.num_resources = ARRAY_SIZE(ls2k_ipmi0_resources),
+		.resources = ls2k_ipmi0_resources
+	},
+	[LS2K_BMC_IPMI1] = {
+		.name = "ls2k-ipmi-si",
+		.num_resources = ARRAY_SIZE(ls2k_ipmi1_resources),
+		.resources = ls2k_ipmi1_resources
+	},
+	[LS2K_BMC_IPMI2] = {
+		.name = "ls2k-ipmi-si",
+		.num_resources = ARRAY_SIZE(ls2k_ipmi2_resources),
+		.resources = ls2k_ipmi2_resources
+	},
+	[LS2K_BMC_IPMI3] = {
+		.name = "ls2k-ipmi-si",
+		.num_resources = ARRAY_SIZE(ls2k_ipmi3_resources),
+		.resources = ls2k_ipmi3_resources
+	},
+	[LS2K_BMC_IPMI4] = {
+		.name = "ls2k-ipmi-si",
+		.num_resources = ARRAY_SIZE(ls2k_ipmi4_resources),
+		.resources = ls2k_ipmi4_resources
+	},
+};
+
+/*
+ * Currently the Loongson-2K BMC hardware does not have an I2C interface to adapt to the
+ * resolution. We set the resolution by presetting "video=1280x1024-16@2M" to the BMC memory.
+ */
+static int ls2k_bmc_parse_mode(struct pci_dev *pdev, struct simplefb_platform_data *pd)
+{
+	char *mode;
+	int depth, ret;
+
+	/* The last 16M of PCI BAR0 is used to store the resolution string. */
+	mode = devm_ioremap(&pdev->dev, pci_resource_start(pdev, 0) + SZ_16M, SZ_16M);
+	if (!mode)
+		return -ENOMEM;
+
+	/* The resolution field starts with the flag "video=". */
+	if (!strncmp(mode, "video=", 6))
+		mode = mode + 6;
+
+	ret = kstrtoint(strsep(&mode, "x"), 10, &pd->width);
+	if (ret)
+		return ret;
+
+	ret = kstrtoint(strsep(&mode, "-"), 10, &pd->height);
+	if (ret)
+		return ret;
+
+	ret = kstrtoint(strsep(&mode, "@"), 10, &depth);
+	if (ret)
+		return ret;
+
+	pd->stride = pd->width * depth / 8;
+	pd->format = depth == 32 ? "a8r8g8b8" : "r5g6b5";
+
+	return 0;
+}
+
+static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
+{
+	struct simplefb_platform_data pd;
+	resource_size_t base;
+	int ret;
+
+	ret = pci_enable_device(dev);
+	if (ret)
+		return ret;
+
+	ret = ls2k_bmc_parse_mode(dev, &pd);
+	if (ret)
+		goto disable_pci;
+
+	ls2k_bmc_cells[LS2K_BMC_DISPLAY].platform_data = &pd;
+	ls2k_bmc_cells[LS2K_BMC_DISPLAY].pdata_size = sizeof(pd);
+	base = dev->resource[0].start + LS2K_DISPLAY_RES_START;
+
+	/* Remove conflicting efifb device */
+	ret = aperture_remove_conflicting_devices(base, SZ_4M, "simple-framebuffer");
+	if (ret) {
+		dev_err(&dev->dev, "Failed to removed firmware framebuffers: %d\n", ret);
+		goto disable_pci;
+	}
+
+	return devm_mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO,
+				    ls2k_bmc_cells, ARRAY_SIZE(ls2k_bmc_cells),
+				    &dev->resource[0], 0, NULL);
+
+disable_pci:
+	pci_disable_device(dev);
+	return ret;
+}
+
+static void ls2k_bmc_remove(struct pci_dev *dev)
+{
+	pci_disable_device(dev);
+}
+
+static struct pci_device_id ls2k_bmc_devices[] = {
+	{ PCI_DEVICE(PCI_VENDOR_ID_LOONGSON, 0x1a05) },
+	{ }
+};
+MODULE_DEVICE_TABLE(pci, ls2k_bmc_devices);
+
+static struct pci_driver ls2k_bmc_driver = {
+	.name = "ls2k-bmc",
+	.id_table = ls2k_bmc_devices,
+	.probe = ls2k_bmc_probe,
+	.remove = ls2k_bmc_remove,
+};
+module_pci_driver(ls2k_bmc_driver);
+
+MODULE_DESCRIPTION("Loongson-2K Board Management Controller (BMC) Core driver");
+MODULE_AUTHOR("Loongson Technology Corporation Limited");
+MODULE_LICENSE("GPL");
-- 
2.47.3

Re: [PATCH v10 1/3] mfd: ls2kbmc: Introduce Loongson-2K BMC core driver

[Lee Jones]

On Fri, 22 Aug 2025, Binbin Zhou wrote:

> The Loongson-2K Board Management Controller provides an PCIe interface
> to the host to access the feature implemented in the BMC.
> 
> The BMC is assembled on a server similar to the server machine with
> Loongson-3 CPU. It supports multiple sub-devices like DRM and IPMI.
> 
> Co-developed-by: Chong Qiao <qiaochong@loongson.cn>
> Signed-off-by: Chong Qiao <qiaochong@loongson.cn>
> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
> Acked-by: Corey Minyard <corey@minyard.net>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>

Looks good.

-- 
Lee Jones [李琼斯]

[PATCH v10 2/3] mfd: ls2kbmc: Add Loongson-2K BMC reset function support

[Binbin Zhou]

Since the display is a sub-function of the Loongson-2K BMC, when the
BMC reset, the entire BMC PCIe is disconnected, including the display
which is interrupted.

Quick overview of the entire LS2K BMC reset process:

There are two types of reset methods: soft reset (BMC-initiated reboot
of IPMI reset command) and BMC watchdog reset (watchdog timeout).

First, regardless of the method, an interrupt is generated (PCIe interrupt
for soft reset/GPIO interrupt for watchdog reset);

Second, during the interrupt process, the system enters bmc_reset_work,
clears the bus/IO/mem resources of the LS7A PCI-E bridge, waits for the BMC
reset to begin, then restores the parent device's PCI configuration space,
waits for the BMC reset to complete, and finally restores the BMC PCI
configuration space.

Display restoration occurs last.

Co-developed-by: Chong Qiao <qiaochong@loongson.cn>
Signed-off-by: Chong Qiao <qiaochong@loongson.cn>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Acked-by: Corey Minyard <corey@minyard.net>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
 drivers/mfd/ls2k-bmc-core.c | 336 ++++++++++++++++++++++++++++++++++++
 1 file changed, 336 insertions(+)

diff --git a/drivers/mfd/ls2k-bmc-core.c b/drivers/mfd/ls2k-bmc-core.c
index 39cc481d9ba1..fa7f1a822076 100644
--- a/drivers/mfd/ls2k-bmc-core.c
+++ b/drivers/mfd/ls2k-bmc-core.c
@@ -10,8 +10,12 @@
  */
 
 #include <linux/aperture.h>
+#include <linux/bitfield.h>
+#include <linux/delay.h>
 #include <linux/errno.h>
 #include <linux/init.h>
+#include <linux/iopoll.h>
+#include <linux/kbd_kern.h>
 #include <linux/kernel.h>
 #include <linux/mfd/core.h>
 #include <linux/module.h>
@@ -19,6 +23,8 @@
 #include <linux/pci_ids.h>
 #include <linux/platform_data/simplefb.h>
 #include <linux/platform_device.h>
+#include <linux/stop_machine.h>
+#include <linux/vt_kern.h>
 
 /* LS2K BMC resources */
 #define LS2K_DISPLAY_RES_START		(SZ_16M + SZ_2M)
@@ -29,6 +35,48 @@
 #define LS2K_IPMI3_RES_START		(LS2K_IPMI2_RES_START + LS2K_IPMI_RES_SIZE)
 #define LS2K_IPMI4_RES_START		(LS2K_IPMI3_RES_START + LS2K_IPMI_RES_SIZE)
 
+#define LS7A_PCI_CFG_SIZE		0x100
+
+/* LS7A bridge registers */
+#define LS7A_PCIE_PORT_CTL0		0x0
+#define LS7A_PCIE_PORT_STS1		0xC
+#define LS7A_GEN2_CTL			0x80C
+#define LS7A_SYMBOL_TIMER		0x71C
+
+/* Bits of LS7A_PCIE_PORT_CTL0 */
+#define LS2K_BMC_PCIE_LTSSM_ENABLE	BIT(3)
+
+/* Bits of LS7A_PCIE_PORT_STS1 */
+#define LS2K_BMC_PCIE_LTSSM_STS		GENMASK(5, 0)
+#define LS2K_BMC_PCIE_CONNECTED		0x11
+
+#define LS2K_BMC_PCIE_DELAY_US		1000
+#define LS2K_BMC_PCIE_TIMEOUT_US	1000000
+
+/* Bits of LS7A_GEN2_CTL */
+#define LS7A_GEN2_SPEED_CHANG		BIT(17)
+#define LS7A_CONF_PHY_TX		BIT(18)
+
+/* Bits of LS7A_SYMBOL_TIMER */
+#define LS7A_MASK_LEN_MATCH		BIT(26)
+
+/* Interval between interruptions */
+#define LS2K_BMC_INT_INTERVAL		(60 * HZ)
+
+/* Maximum time to wait for U-Boot and DDR to be ready with ms. */
+#define LS2K_BMC_RESET_WAIT_TIME	10000
+
+/* It's an experience value */
+#define LS7A_BAR0_CHECK_MAX_TIMES	2000
+
+#define LS2K_BMC_RESET_GPIO		14
+#define LOONGSON_GPIO_REG_BASE		0x1FE00500
+#define LOONGSON_GPIO_REG_SIZE		0x18
+#define LOONGSON_GPIO_OEN		0x0
+#define LOONGSON_GPIO_FUNC		0x4
+#define LOONGSON_GPIO_INTPOL		0x10
+#define LOONGSON_GPIO_INTEN		0x14
+
 enum {
 	LS2K_BMC_DISPLAY,
 	LS2K_BMC_IPMI0,
@@ -95,6 +143,281 @@ static struct mfd_cell ls2k_bmc_cells[] = {
 	},
 };
 
+/* Index of the BMC PCI configuration space to be restored at BMC reset. */
+struct ls2k_bmc_pci_data {
+	u32 pci_command;
+	u32 base_address0;
+	u32 interrupt_line;
+};
+
+/* Index of the parent PCI configuration space to be restored at BMC reset. */
+struct ls2k_bmc_bridge_pci_data {
+	u32 pci_command;
+	u32 base_address[6];
+	u32 rom_addreess;
+	u32 interrupt_line;
+	u32 msi_hi;
+	u32 msi_lo;
+	u32 devctl;
+	u32 linkcap;
+	u32 linkctl_sts;
+	u32 symbol_timer;
+	u32 gen2_ctrl;
+};
+
+struct ls2k_bmc_pdata {
+	struct device *dev;
+	struct work_struct bmc_reset_work;
+	struct ls2k_bmc_pci_data bmc_pci_data;
+	struct ls2k_bmc_bridge_pci_data bridge_pci_data;
+};
+
+static bool ls2k_bmc_bar0_addr_is_set(struct pci_dev *pdev)
+{
+	u32 addr;
+
+	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);
+
+	return addr & PCI_BASE_ADDRESS_MEM_MASK ? true : false;
+}
+
+static bool ls2k_bmc_pcie_is_connected(struct pci_dev *parent, struct ls2k_bmc_pdata *ddata)
+{
+	void __iomem *base;
+	int val, ret;
+
+	base = pci_iomap(parent, 0, LS7A_PCI_CFG_SIZE);
+	if (!base)
+		return false;
+
+	val = readl(base + LS7A_PCIE_PORT_CTL0);
+	writel(val | LS2K_BMC_PCIE_LTSSM_ENABLE, base + LS7A_PCIE_PORT_CTL0);
+
+	ret = readl_poll_timeout_atomic(base + LS7A_PCIE_PORT_STS1, val,
+					(val & LS2K_BMC_PCIE_LTSSM_STS) == LS2K_BMC_PCIE_CONNECTED,
+					LS2K_BMC_PCIE_DELAY_US, LS2K_BMC_PCIE_TIMEOUT_US);
+	if (ret) {
+		pci_iounmap(parent, base);
+		dev_err(ddata->dev, "PCI-E training failed status=0x%x\n", val);
+		return false;
+	}
+
+	pci_iounmap(parent, base);
+	return true;
+}
+
+static void ls2k_bmc_restore_bridge_pci_data(struct pci_dev *parent, struct ls2k_bmc_pdata *ddata)
+{
+	int base, i = 0;
+
+	pci_write_config_dword(parent, PCI_COMMAND, ddata->bridge_pci_data.pci_command);
+
+	for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += 4, i++)
+		pci_write_config_dword(parent, base, ddata->bridge_pci_data.base_address[i]);
+
+	pci_write_config_dword(parent, PCI_ROM_ADDRESS, ddata->bridge_pci_data.rom_addreess);
+	pci_write_config_dword(parent, PCI_INTERRUPT_LINE, ddata->bridge_pci_data.interrupt_line);
+
+	pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO,
+			       ddata->bridge_pci_data.msi_lo);
+	pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI,
+			       ddata->bridge_pci_data.msi_hi);
+	pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL,
+			       ddata->bridge_pci_data.devctl);
+	pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP,
+			       ddata->bridge_pci_data.linkcap);
+	pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL,
+			       ddata->bridge_pci_data.linkctl_sts);
+
+	pci_write_config_dword(parent, LS7A_GEN2_CTL, ddata->bridge_pci_data.gen2_ctrl);
+	pci_write_config_dword(parent, LS7A_SYMBOL_TIMER, ddata->bridge_pci_data.symbol_timer);
+}
+
+static int ls2k_bmc_recover_pci_data(void *data)
+{
+	struct ls2k_bmc_pdata *ddata = data;
+	struct pci_dev *pdev = to_pci_dev(ddata->dev);
+	struct pci_dev *parent = pdev->bus->self;
+	u32 i;
+
+	/*
+	 * Clear the bus, io and mem resources of the PCI-E bridge to zero, so that
+	 * the processor can not access the LS2K PCI-E port, to avoid crashing due to
+	 * the lack of return signal from accessing the LS2K PCI-E port.
+	 */
+	pci_write_config_dword(parent, PCI_BASE_ADDRESS_2, 0);
+	pci_write_config_dword(parent, PCI_BASE_ADDRESS_3, 0);
+	pci_write_config_dword(parent, PCI_BASE_ADDRESS_4, 0);
+
+	/*
+	 * When the LS2K BMC is reset, the LS7A PCI-E port is also reset, and its PCI
+	 * BAR0 register is cleared. Due to the time gap between the GPIO interrupt
+	 * generation and the LS2K BMC reset, the LS7A PCI BAR0 register is read to
+	 * determine whether the reset has begun.
+	 */
+	for (i = LS7A_BAR0_CHECK_MAX_TIMES; i > 0 ; i--) {
+		if (!ls2k_bmc_bar0_addr_is_set(parent))
+			break;
+		mdelay(1);
+	};
+
+	if (i == 0)
+		return false;
+
+	ls2k_bmc_restore_bridge_pci_data(parent, ddata);
+
+	/* Check if PCI-E is connected */
+	if (!ls2k_bmc_pcie_is_connected(parent, ddata))
+		return false;
+
+	/* Waiting for U-Boot and DDR ready */
+	mdelay(LS2K_BMC_RESET_WAIT_TIME);
+	if (!ls2k_bmc_bar0_addr_is_set(parent))
+		return false;
+
+	/* Restore LS2K BMC PCI-E config data */
+	pci_write_config_dword(pdev, PCI_COMMAND, ddata->bmc_pci_data.pci_command);
+	pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, ddata->bmc_pci_data.base_address0);
+	pci_write_config_dword(pdev, PCI_INTERRUPT_LINE, ddata->bmc_pci_data.interrupt_line);
+
+	return 0;
+}
+
+static void ls2k_bmc_events_fn(struct work_struct *work)
+{
+	struct ls2k_bmc_pdata *ddata = container_of(work, struct ls2k_bmc_pdata, bmc_reset_work);
+
+	/*
+	 * The PCI-E is lost when the BMC resets, at which point access to the PCI-E
+	 * from other CPUs is suspended to prevent a crash.
+	 */
+	stop_machine(ls2k_bmc_recover_pci_data, ddata, NULL);
+
+	if (IS_ENABLED(CONFIG_VT)) {
+		/* Re-push the display due to previous PCI-E loss. */
+		set_console(vt_move_to_console(MAX_NR_CONSOLES - 1, 1));
+	}
+}
+
+static irqreturn_t ls2k_bmc_interrupt(int irq, void *arg)
+{
+	struct ls2k_bmc_pdata *ddata = arg;
+	static unsigned long last_jiffies;
+
+	if (system_state != SYSTEM_RUNNING)
+		return IRQ_HANDLED;
+
+	/* Skip interrupt in LS2K_BMC_INT_INTERVAL */
+	if (time_after(jiffies, last_jiffies + LS2K_BMC_INT_INTERVAL)) {
+		schedule_work(&ddata->bmc_reset_work);
+		last_jiffies = jiffies;
+	}
+
+	return IRQ_HANDLED;
+}
+
+/*
+ * Saves the BMC parent device (LS7A) and its own PCI configuration space registers
+ * that need to be restored after BMC reset.
+ */
+static void ls2k_bmc_save_pci_data(struct pci_dev *pdev, struct ls2k_bmc_pdata *ddata)
+{
+	struct pci_dev *parent = pdev->bus->self;
+	int base, i = 0;
+
+	pci_read_config_dword(parent, PCI_COMMAND, &ddata->bridge_pci_data.pci_command);
+
+	for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += 4, i++)
+		pci_read_config_dword(parent, base, &ddata->bridge_pci_data.base_address[i]);
+
+	pci_read_config_dword(parent, PCI_ROM_ADDRESS, &ddata->bridge_pci_data.rom_addreess);
+	pci_read_config_dword(parent, PCI_INTERRUPT_LINE, &ddata->bridge_pci_data.interrupt_line);
+
+	pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO,
+			      &ddata->bridge_pci_data.msi_lo);
+	pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI,
+			      &ddata->bridge_pci_data.msi_hi);
+
+	pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL,
+			      &ddata->bridge_pci_data.devctl);
+	pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP,
+			      &ddata->bridge_pci_data.linkcap);
+	pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL,
+			      &ddata->bridge_pci_data.linkctl_sts);
+
+	pci_read_config_dword(parent, LS7A_GEN2_CTL, &ddata->bridge_pci_data.gen2_ctrl);
+	ddata->bridge_pci_data.gen2_ctrl |= FIELD_PREP(LS7A_GEN2_SPEED_CHANG, 0x1)
+					| FIELD_PREP(LS7A_CONF_PHY_TX, 0x0);
+
+	pci_read_config_dword(parent, LS7A_SYMBOL_TIMER, &ddata->bridge_pci_data.symbol_timer);
+	ddata->bridge_pci_data.symbol_timer |= LS7A_MASK_LEN_MATCH;
+
+	pci_read_config_dword(pdev, PCI_COMMAND, &ddata->bmc_pci_data.pci_command);
+	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &ddata->bmc_pci_data.base_address0);
+	pci_read_config_dword(pdev, PCI_INTERRUPT_LINE, &ddata->bmc_pci_data.interrupt_line);
+}
+
+static int ls2k_bmc_pdata_initial(struct ls2k_bmc_pdata *ddata)
+{
+	struct pci_dev *pdev = to_pci_dev(ddata->dev);
+	int gsi = 16 + (LS2K_BMC_RESET_GPIO & 7);
+	void __iomem *gpio_base;
+	int irq, ret, val;
+
+	ls2k_bmc_save_pci_data(pdev, ddata);
+
+	INIT_WORK(&ddata->bmc_reset_work, ls2k_bmc_events_fn);
+
+	ret = devm_request_irq(&pdev->dev, pdev->irq, ls2k_bmc_interrupt,
+			       IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc pcie", ddata);
+	if (ret) {
+		dev_err(ddata->dev, "Failed to request LS2KBMC PCI-E IRQ %d.\n", pdev->irq);
+		return ret;
+	}
+
+	/*
+	 * Since gpio_chip->to_irq is not implemented in the Loongson-3 GPIO driver,
+	 * acpi_register_gsi() is used to obtain the GPIO IRQ. The GPIO interrupt is a
+	 * watchdog interrupt that is triggered when the BMC resets.
+	 */
+	irq = acpi_register_gsi(NULL, gsi, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW);
+	if (irq < 0)
+		return irq;
+
+	gpio_base = ioremap(LOONGSON_GPIO_REG_BASE, LOONGSON_GPIO_REG_SIZE);
+	if (!gpio_base) {
+		ret = -ENOMEM;
+		goto acpi_failed;
+	}
+
+	/* Disable GPIO output */
+	val = readl(gpio_base + LOONGSON_GPIO_OEN);
+	writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_OEN);
+
+	/* Enable GPIO functionality */
+	val = readl(gpio_base + LOONGSON_GPIO_FUNC);
+	writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_FUNC);
+
+	/* Set GPIO interrupts to low-level active */
+	val = readl(gpio_base + LOONGSON_GPIO_INTPOL);
+	writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTPOL);
+
+	/* Enable GPIO interrupts */
+	val = readl(gpio_base + LOONGSON_GPIO_INTEN);
+	writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTEN);
+
+	ret = devm_request_irq(ddata->dev, irq, ls2k_bmc_interrupt,
+			       IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc gpio", ddata);
+	if (ret)
+		dev_err(ddata->dev, "Failed to request LS2KBMC GPIO IRQ %d.\n", irq);
+
+	iounmap(gpio_base);
+
+acpi_failed:
+	acpi_unregister_gsi(gsi);
+	return ret;
+}
+
 /*
  * Currently the Loongson-2K BMC hardware does not have an I2C interface to adapt to the
  * resolution. We set the resolution by presetting "video=1280x1024-16@2M" to the BMC memory.
@@ -134,6 +457,7 @@ static int ls2k_bmc_parse_mode(struct pci_dev *pdev, struct simplefb_platform_da
 static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
 {
 	struct simplefb_platform_data pd;
+	struct ls2k_bmc_pdata *ddata;
 	resource_size_t base;
 	int ret;
 
@@ -141,6 +465,18 @@ static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
 	if (ret)
 		return ret;
 
+	ddata = devm_kzalloc(&dev->dev, sizeof(*ddata), GFP_KERNEL);
+	if (IS_ERR(ddata)) {
+		ret = -ENOMEM;
+		goto disable_pci;
+	}
+
+	ddata->dev = &dev->dev;
+
+	ret = ls2k_bmc_pdata_initial(ddata);
+	if (ret)
+		goto disable_pci;
+
 	ret = ls2k_bmc_parse_mode(dev, &pd);
 	if (ret)
 		goto disable_pci;
-- 
2.47.3

Re: [PATCH v10 2/3] mfd: ls2kbmc: Add Loongson-2K BMC reset function support

[Lee Jones]

On Fri, 22 Aug 2025, Binbin Zhou wrote:

> Since the display is a sub-function of the Loongson-2K BMC, when the
> BMC reset, the entire BMC PCIe is disconnected, including the display
> which is interrupted.
> 
> Quick overview of the entire LS2K BMC reset process:
> 
> There are two types of reset methods: soft reset (BMC-initiated reboot
> of IPMI reset command) and BMC watchdog reset (watchdog timeout).
> 
> First, regardless of the method, an interrupt is generated (PCIe interrupt
> for soft reset/GPIO interrupt for watchdog reset);
> 
> Second, during the interrupt process, the system enters bmc_reset_work,
> clears the bus/IO/mem resources of the LS7A PCI-E bridge, waits for the BMC
> reset to begin, then restores the parent device's PCI configuration space,
> waits for the BMC reset to complete, and finally restores the BMC PCI
> configuration space.
> 
> Display restoration occurs last.
> 
> Co-developed-by: Chong Qiao <qiaochong@loongson.cn>
> Signed-off-by: Chong Qiao <qiaochong@loongson.cn>
> Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
> Acked-by: Corey Minyard <corey@minyard.net>
> Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> ---
>  drivers/mfd/ls2k-bmc-core.c | 336 ++++++++++++++++++++++++++++++++++++
>  1 file changed, 336 insertions(+)

Couple of nits to finish up:

> diff --git a/drivers/mfd/ls2k-bmc-core.c b/drivers/mfd/ls2k-bmc-core.c
> index 39cc481d9ba1..fa7f1a822076 100644
> --- a/drivers/mfd/ls2k-bmc-core.c
> +++ b/drivers/mfd/ls2k-bmc-core.c
> @@ -10,8 +10,12 @@
>   */
>  
>  #include <linux/aperture.h>
> +#include <linux/bitfield.h>
> +#include <linux/delay.h>
>  #include <linux/errno.h>
>  #include <linux/init.h>
> +#include <linux/iopoll.h>
> +#include <linux/kbd_kern.h>
>  #include <linux/kernel.h>
>  #include <linux/mfd/core.h>
>  #include <linux/module.h>
> @@ -19,6 +23,8 @@
>  #include <linux/pci_ids.h>
>  #include <linux/platform_data/simplefb.h>
>  #include <linux/platform_device.h>
> +#include <linux/stop_machine.h>
> +#include <linux/vt_kern.h>
>  
>  /* LS2K BMC resources */
>  #define LS2K_DISPLAY_RES_START		(SZ_16M + SZ_2M)
> @@ -29,6 +35,48 @@
>  #define LS2K_IPMI3_RES_START		(LS2K_IPMI2_RES_START + LS2K_IPMI_RES_SIZE)
>  #define LS2K_IPMI4_RES_START		(LS2K_IPMI3_RES_START + LS2K_IPMI_RES_SIZE)
>  
> +#define LS7A_PCI_CFG_SIZE		0x100
> +
> +/* LS7A bridge registers */
> +#define LS7A_PCIE_PORT_CTL0		0x0
> +#define LS7A_PCIE_PORT_STS1		0xC
> +#define LS7A_GEN2_CTL			0x80C
> +#define LS7A_SYMBOL_TIMER		0x71C
> +
> +/* Bits of LS7A_PCIE_PORT_CTL0 */
> +#define LS2K_BMC_PCIE_LTSSM_ENABLE	BIT(3)
> +
> +/* Bits of LS7A_PCIE_PORT_STS1 */
> +#define LS2K_BMC_PCIE_LTSSM_STS		GENMASK(5, 0)
> +#define LS2K_BMC_PCIE_CONNECTED		0x11
> +
> +#define LS2K_BMC_PCIE_DELAY_US		1000
> +#define LS2K_BMC_PCIE_TIMEOUT_US	1000000
> +
> +/* Bits of LS7A_GEN2_CTL */
> +#define LS7A_GEN2_SPEED_CHANG		BIT(17)
> +#define LS7A_CONF_PHY_TX		BIT(18)
> +
> +/* Bits of LS7A_SYMBOL_TIMER */
> +#define LS7A_MASK_LEN_MATCH		BIT(26)
> +
> +/* Interval between interruptions */
> +#define LS2K_BMC_INT_INTERVAL		(60 * HZ)
> +
> +/* Maximum time to wait for U-Boot and DDR to be ready with ms. */
> +#define LS2K_BMC_RESET_WAIT_TIME	10000
> +
> +/* It's an experience value */
> +#define LS7A_BAR0_CHECK_MAX_TIMES	2000
> +
> +#define LS2K_BMC_RESET_GPIO		14
> +#define LOONGSON_GPIO_REG_BASE		0x1FE00500
> +#define LOONGSON_GPIO_REG_SIZE		0x18
> +#define LOONGSON_GPIO_OEN		0x0
> +#define LOONGSON_GPIO_FUNC		0x4
> +#define LOONGSON_GPIO_INTPOL		0x10
> +#define LOONGSON_GPIO_INTEN		0x14
> +
>  enum {
>  	LS2K_BMC_DISPLAY,
>  	LS2K_BMC_IPMI0,
> @@ -95,6 +143,281 @@ static struct mfd_cell ls2k_bmc_cells[] = {
>  	},
>  };
>  
> +/* Index of the BMC PCI configuration space to be restored at BMC reset. */
> +struct ls2k_bmc_pci_data {
> +	u32 pci_command;
> +	u32 base_address0;
> +	u32 interrupt_line;
> +};
> +
> +/* Index of the parent PCI configuration space to be restored at BMC reset. */
> +struct ls2k_bmc_bridge_pci_data {
> +	u32 pci_command;
> +	u32 base_address[6];
> +	u32 rom_addreess;
> +	u32 interrupt_line;
> +	u32 msi_hi;
> +	u32 msi_lo;
> +	u32 devctl;
> +	u32 linkcap;
> +	u32 linkctl_sts;
> +	u32 symbol_timer;
> +	u32 gen2_ctrl;
> +};
> +
> +struct ls2k_bmc_pdata {

Drop the pdata part completely.

pdata is something else.

> +	struct device *dev;
> +	struct work_struct bmc_reset_work;
> +	struct ls2k_bmc_pci_data bmc_pci_data;
> +	struct ls2k_bmc_bridge_pci_data bridge_pci_data;
> +};
> +
> +static bool ls2k_bmc_bar0_addr_is_set(struct pci_dev *pdev)
> +{
> +	u32 addr;
> +
> +	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);
> +
> +	return addr & PCI_BASE_ADDRESS_MEM_MASK ? true : false;
> +}
> +
> +static bool ls2k_bmc_pcie_is_connected(struct pci_dev *parent, struct ls2k_bmc_pdata *ddata)
> +{
> +	void __iomem *base;
> +	int val, ret;
> +
> +	base = pci_iomap(parent, 0, LS7A_PCI_CFG_SIZE);
> +	if (!base)
> +		return false;
> +
> +	val = readl(base + LS7A_PCIE_PORT_CTL0);
> +	writel(val | LS2K_BMC_PCIE_LTSSM_ENABLE, base + LS7A_PCIE_PORT_CTL0);
> +
> +	ret = readl_poll_timeout_atomic(base + LS7A_PCIE_PORT_STS1, val,
> +					(val & LS2K_BMC_PCIE_LTSSM_STS) == LS2K_BMC_PCIE_CONNECTED,
> +					LS2K_BMC_PCIE_DELAY_US, LS2K_BMC_PCIE_TIMEOUT_US);
> +	if (ret) {
> +		pci_iounmap(parent, base);
> +		dev_err(ddata->dev, "PCI-E training failed status=0x%x\n", val);
> +		return false;
> +	}
> +
> +	pci_iounmap(parent, base);
> +	return true;
> +}
> +
> +static void ls2k_bmc_restore_bridge_pci_data(struct pci_dev *parent, struct ls2k_bmc_pdata *ddata)
> +{
> +	int base, i = 0;
> +
> +	pci_write_config_dword(parent, PCI_COMMAND, ddata->bridge_pci_data.pci_command);
> +
> +	for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += 4, i++)

Define 4.

> +		pci_write_config_dword(parent, base, ddata->bridge_pci_data.base_address[i]);
> +
> +	pci_write_config_dword(parent, PCI_ROM_ADDRESS, ddata->bridge_pci_data.rom_addreess);
> +	pci_write_config_dword(parent, PCI_INTERRUPT_LINE, ddata->bridge_pci_data.interrupt_line);
> +
> +	pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO,
> +			       ddata->bridge_pci_data.msi_lo);
> +	pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI,
> +			       ddata->bridge_pci_data.msi_hi);
> +	pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL,
> +			       ddata->bridge_pci_data.devctl);
> +	pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP,
> +			       ddata->bridge_pci_data.linkcap);
> +	pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL,
> +			       ddata->bridge_pci_data.linkctl_sts);
> +
> +	pci_write_config_dword(parent, LS7A_GEN2_CTL, ddata->bridge_pci_data.gen2_ctrl);
> +	pci_write_config_dword(parent, LS7A_SYMBOL_TIMER, ddata->bridge_pci_data.symbol_timer);
> +}
> +
> +static int ls2k_bmc_recover_pci_data(void *data)
> +{
> +	struct ls2k_bmc_pdata *ddata = data;
> +	struct pci_dev *pdev = to_pci_dev(ddata->dev);
> +	struct pci_dev *parent = pdev->bus->self;
> +	u32 i;
> +
> +	/*
> +	 * Clear the bus, io and mem resources of the PCI-E bridge to zero, so that
> +	 * the processor can not access the LS2K PCI-E port, to avoid crashing due to
> +	 * the lack of return signal from accessing the LS2K PCI-E port.
> +	 */
> +	pci_write_config_dword(parent, PCI_BASE_ADDRESS_2, 0);
> +	pci_write_config_dword(parent, PCI_BASE_ADDRESS_3, 0);
> +	pci_write_config_dword(parent, PCI_BASE_ADDRESS_4, 0);
> +
> +	/*
> +	 * When the LS2K BMC is reset, the LS7A PCI-E port is also reset, and its PCI
> +	 * BAR0 register is cleared. Due to the time gap between the GPIO interrupt
> +	 * generation and the LS2K BMC reset, the LS7A PCI BAR0 register is read to
> +	 * determine whether the reset has begun.
> +	 */
> +	for (i = LS7A_BAR0_CHECK_MAX_TIMES; i > 0 ; i--) {
> +		if (!ls2k_bmc_bar0_addr_is_set(parent))
> +			break;
> +		mdelay(1);
> +	};
> +
> +	if (i == 0)
> +		return false;
> +
> +	ls2k_bmc_restore_bridge_pci_data(parent, ddata);
> +
> +	/* Check if PCI-E is connected */
> +	if (!ls2k_bmc_pcie_is_connected(parent, ddata))
> +		return false;
> +
> +	/* Waiting for U-Boot and DDR ready */
> +	mdelay(LS2K_BMC_RESET_WAIT_TIME);
> +	if (!ls2k_bmc_bar0_addr_is_set(parent))
> +		return false;
> +
> +	/* Restore LS2K BMC PCI-E config data */
> +	pci_write_config_dword(pdev, PCI_COMMAND, ddata->bmc_pci_data.pci_command);
> +	pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, ddata->bmc_pci_data.base_address0);
> +	pci_write_config_dword(pdev, PCI_INTERRUPT_LINE, ddata->bmc_pci_data.interrupt_line);
> +
> +	return 0;
> +}
> +
> +static void ls2k_bmc_events_fn(struct work_struct *work)
> +{
> +	struct ls2k_bmc_pdata *ddata = container_of(work, struct ls2k_bmc_pdata, bmc_reset_work);
> +
> +	/*
> +	 * The PCI-E is lost when the BMC resets, at which point access to the PCI-E
> +	 * from other CPUs is suspended to prevent a crash.
> +	 */
> +	stop_machine(ls2k_bmc_recover_pci_data, ddata, NULL);
> +
> +	if (IS_ENABLED(CONFIG_VT)) {
> +		/* Re-push the display due to previous PCI-E loss. */
> +		set_console(vt_move_to_console(MAX_NR_CONSOLES - 1, 1));
> +	}
> +}
> +
> +static irqreturn_t ls2k_bmc_interrupt(int irq, void *arg)
> +{
> +	struct ls2k_bmc_pdata *ddata = arg;
> +	static unsigned long last_jiffies;
> +
> +	if (system_state != SYSTEM_RUNNING)
> +		return IRQ_HANDLED;
> +
> +	/* Skip interrupt in LS2K_BMC_INT_INTERVAL */
> +	if (time_after(jiffies, last_jiffies + LS2K_BMC_INT_INTERVAL)) {
> +		schedule_work(&ddata->bmc_reset_work);
> +		last_jiffies = jiffies;
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +/*
> + * Saves the BMC parent device (LS7A) and its own PCI configuration space registers
> + * that need to be restored after BMC reset.
> + */
> +static void ls2k_bmc_save_pci_data(struct pci_dev *pdev, struct ls2k_bmc_pdata *ddata)
> +{
> +	struct pci_dev *parent = pdev->bus->self;
> +	int base, i = 0;
> +
> +	pci_read_config_dword(parent, PCI_COMMAND, &ddata->bridge_pci_data.pci_command);
> +
> +	for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += 4, i++)
> +		pci_read_config_dword(parent, base, &ddata->bridge_pci_data.base_address[i]);
> +
> +	pci_read_config_dword(parent, PCI_ROM_ADDRESS, &ddata->bridge_pci_data.rom_addreess);
> +	pci_read_config_dword(parent, PCI_INTERRUPT_LINE, &ddata->bridge_pci_data.interrupt_line);
> +
> +	pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO,
> +			      &ddata->bridge_pci_data.msi_lo);
> +	pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI,
> +			      &ddata->bridge_pci_data.msi_hi);
> +
> +	pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL,
> +			      &ddata->bridge_pci_data.devctl);
> +	pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP,
> +			      &ddata->bridge_pci_data.linkcap);
> +	pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL,
> +			      &ddata->bridge_pci_data.linkctl_sts);
> +
> +	pci_read_config_dword(parent, LS7A_GEN2_CTL, &ddata->bridge_pci_data.gen2_ctrl);
> +	ddata->bridge_pci_data.gen2_ctrl |= FIELD_PREP(LS7A_GEN2_SPEED_CHANG, 0x1)
> +					| FIELD_PREP(LS7A_CONF_PHY_TX, 0x0);
> +
> +	pci_read_config_dword(parent, LS7A_SYMBOL_TIMER, &ddata->bridge_pci_data.symbol_timer);
> +	ddata->bridge_pci_data.symbol_timer |= LS7A_MASK_LEN_MATCH;
> +
> +	pci_read_config_dword(pdev, PCI_COMMAND, &ddata->bmc_pci_data.pci_command);
> +	pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &ddata->bmc_pci_data.base_address0);
> +	pci_read_config_dword(pdev, PCI_INTERRUPT_LINE, &ddata->bmc_pci_data.interrupt_line);
> +}
> +
> +static int ls2k_bmc_pdata_initial(struct ls2k_bmc_pdata *ddata)

What are you actually doing here exactly.

I don't think "pdata_initial" describes it.

> +{
> +	struct pci_dev *pdev = to_pci_dev(ddata->dev);
> +	int gsi = 16 + (LS2K_BMC_RESET_GPIO & 7);

Define 16.

> +	void __iomem *gpio_base;
> +	int irq, ret, val;
> +
> +	ls2k_bmc_save_pci_data(pdev, ddata);
> +
> +	INIT_WORK(&ddata->bmc_reset_work, ls2k_bmc_events_fn);
> +
> +	ret = devm_request_irq(&pdev->dev, pdev->irq, ls2k_bmc_interrupt,
> +			       IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc pcie", ddata);
> +	if (ret) {
> +		dev_err(ddata->dev, "Failed to request LS2KBMC PCI-E IRQ %d.\n", pdev->irq);
> +		return ret;
> +	}
> +
> +	/*
> +	 * Since gpio_chip->to_irq is not implemented in the Loongson-3 GPIO driver,
> +	 * acpi_register_gsi() is used to obtain the GPIO IRQ. The GPIO interrupt is a
> +	 * watchdog interrupt that is triggered when the BMC resets.
> +	 */
> +	irq = acpi_register_gsi(NULL, gsi, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW);
> +	if (irq < 0)
> +		return irq;
> +
> +	gpio_base = ioremap(LOONGSON_GPIO_REG_BASE, LOONGSON_GPIO_REG_SIZE);
> +	if (!gpio_base) {
> +		ret = -ENOMEM;
> +		goto acpi_failed;
> +	}
> +
> +	/* Disable GPIO output */
> +	val = readl(gpio_base + LOONGSON_GPIO_OEN);
> +	writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_OEN);
> +
> +	/* Enable GPIO functionality */
> +	val = readl(gpio_base + LOONGSON_GPIO_FUNC);
> +	writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_FUNC);
> +
> +	/* Set GPIO interrupts to low-level active */
> +	val = readl(gpio_base + LOONGSON_GPIO_INTPOL);
> +	writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTPOL);
> +
> +	/* Enable GPIO interrupts */
> +	val = readl(gpio_base + LOONGSON_GPIO_INTEN);
> +	writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTEN);
> +
> +	ret = devm_request_irq(ddata->dev, irq, ls2k_bmc_interrupt,
> +			       IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc gpio", ddata);
> +	if (ret)
> +		dev_err(ddata->dev, "Failed to request LS2KBMC GPIO IRQ %d.\n", irq);
> +
> +	iounmap(gpio_base);
> +
> +acpi_failed:
> +	acpi_unregister_gsi(gsi);
> +	return ret;
> +}
> +
>  /*
>   * Currently the Loongson-2K BMC hardware does not have an I2C interface to adapt to the
>   * resolution. We set the resolution by presetting "video=1280x1024-16@2M" to the BMC memory.
> @@ -134,6 +457,7 @@ static int ls2k_bmc_parse_mode(struct pci_dev *pdev, struct simplefb_platform_da
>  static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
>  {
>  	struct simplefb_platform_data pd;
> +	struct ls2k_bmc_pdata *ddata;
>  	resource_size_t base;
>  	int ret;
>  
> @@ -141,6 +465,18 @@ static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
>  	if (ret)
>  		return ret;
>  
> +	ddata = devm_kzalloc(&dev->dev, sizeof(*ddata), GFP_KERNEL);
> +	if (IS_ERR(ddata)) {
> +		ret = -ENOMEM;
> +		goto disable_pci;
> +	}
> +
> +	ddata->dev = &dev->dev;
> +
> +	ret = ls2k_bmc_pdata_initial(ddata);
> +	if (ret)
> +		goto disable_pci;
> +
>  	ret = ls2k_bmc_parse_mode(dev, &pd);
>  	if (ret)
>  		goto disable_pci;
> -- 
> 2.47.3
> 

-- 
Lee Jones [李琼斯]

Re: [PATCH v10 2/3] mfd: ls2kbmc: Add Loongson-2K BMC reset function support

[Binbin Zhou]

Hi Lee:

Thanks for your reply.

On Tue, Sep 2, 2025 at 10:46 PM Lee Jones <lee@kernel.org> wrote:
>
> On Fri, 22 Aug 2025, Binbin Zhou wrote:
>
> > Since the display is a sub-function of the Loongson-2K BMC, when the
> > BMC reset, the entire BMC PCIe is disconnected, including the display
> > which is interrupted.
> >
> > Quick overview of the entire LS2K BMC reset process:
> >
> > There are two types of reset methods: soft reset (BMC-initiated reboot
> > of IPMI reset command) and BMC watchdog reset (watchdog timeout).
> >
> > First, regardless of the method, an interrupt is generated (PCIe interrupt
> > for soft reset/GPIO interrupt for watchdog reset);
> >
> > Second, during the interrupt process, the system enters bmc_reset_work,
> > clears the bus/IO/mem resources of the LS7A PCI-E bridge, waits for the BMC
> > reset to begin, then restores the parent device's PCI configuration space,
> > waits for the BMC reset to complete, and finally restores the BMC PCI
> > configuration space.
> >
> > Display restoration occurs last.
> >
> > Co-developed-by: Chong Qiao <qiaochong@loongson.cn>
> > Signed-off-by: Chong Qiao <qiaochong@loongson.cn>
> > Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
> > Acked-by: Corey Minyard <corey@minyard.net>
> > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > ---
> >  drivers/mfd/ls2k-bmc-core.c | 336 ++++++++++++++++++++++++++++++++++++
> >  1 file changed, 336 insertions(+)
>
> Couple of nits to finish up:
>
> > diff --git a/drivers/mfd/ls2k-bmc-core.c b/drivers/mfd/ls2k-bmc-core.c
> > index 39cc481d9ba1..fa7f1a822076 100644
> > --- a/drivers/mfd/ls2k-bmc-core.c
> > +++ b/drivers/mfd/ls2k-bmc-core.c
> > @@ -10,8 +10,12 @@
> >   */
> >
> >  #include <linux/aperture.h>
> > +#include <linux/bitfield.h>
> > +#include <linux/delay.h>
> >  #include <linux/errno.h>
> >  #include <linux/init.h>
> > +#include <linux/iopoll.h>
> > +#include <linux/kbd_kern.h>
> >  #include <linux/kernel.h>
> >  #include <linux/mfd/core.h>
> >  #include <linux/module.h>
> > @@ -19,6 +23,8 @@
> >  #include <linux/pci_ids.h>
> >  #include <linux/platform_data/simplefb.h>
> >  #include <linux/platform_device.h>
> > +#include <linux/stop_machine.h>
> > +#include <linux/vt_kern.h>
> >
> >  /* LS2K BMC resources */
> >  #define LS2K_DISPLAY_RES_START               (SZ_16M + SZ_2M)
> > @@ -29,6 +35,48 @@
> >  #define LS2K_IPMI3_RES_START         (LS2K_IPMI2_RES_START + LS2K_IPMI_RES_SIZE)
> >  #define LS2K_IPMI4_RES_START         (LS2K_IPMI3_RES_START + LS2K_IPMI_RES_SIZE)
> >
> > +#define LS7A_PCI_CFG_SIZE            0x100
> > +
> > +/* LS7A bridge registers */
> > +#define LS7A_PCIE_PORT_CTL0          0x0
> > +#define LS7A_PCIE_PORT_STS1          0xC
> > +#define LS7A_GEN2_CTL                        0x80C
> > +#define LS7A_SYMBOL_TIMER            0x71C
> > +
> > +/* Bits of LS7A_PCIE_PORT_CTL0 */
> > +#define LS2K_BMC_PCIE_LTSSM_ENABLE   BIT(3)
> > +
> > +/* Bits of LS7A_PCIE_PORT_STS1 */
> > +#define LS2K_BMC_PCIE_LTSSM_STS              GENMASK(5, 0)
> > +#define LS2K_BMC_PCIE_CONNECTED              0x11
> > +
> > +#define LS2K_BMC_PCIE_DELAY_US               1000
> > +#define LS2K_BMC_PCIE_TIMEOUT_US     1000000
> > +
> > +/* Bits of LS7A_GEN2_CTL */
> > +#define LS7A_GEN2_SPEED_CHANG                BIT(17)
> > +#define LS7A_CONF_PHY_TX             BIT(18)
> > +
> > +/* Bits of LS7A_SYMBOL_TIMER */
> > +#define LS7A_MASK_LEN_MATCH          BIT(26)
> > +
> > +/* Interval between interruptions */
> > +#define LS2K_BMC_INT_INTERVAL                (60 * HZ)
> > +
> > +/* Maximum time to wait for U-Boot and DDR to be ready with ms. */
> > +#define LS2K_BMC_RESET_WAIT_TIME     10000
> > +
> > +/* It's an experience value */
> > +#define LS7A_BAR0_CHECK_MAX_TIMES    2000
> > +
> > +#define LS2K_BMC_RESET_GPIO          14
> > +#define LOONGSON_GPIO_REG_BASE               0x1FE00500
> > +#define LOONGSON_GPIO_REG_SIZE               0x18
> > +#define LOONGSON_GPIO_OEN            0x0
> > +#define LOONGSON_GPIO_FUNC           0x4
> > +#define LOONGSON_GPIO_INTPOL         0x10
> > +#define LOONGSON_GPIO_INTEN          0x14
> > +
> >  enum {
> >       LS2K_BMC_DISPLAY,
> >       LS2K_BMC_IPMI0,
> > @@ -95,6 +143,281 @@ static struct mfd_cell ls2k_bmc_cells[] = {
> >       },
> >  };
> >
> > +/* Index of the BMC PCI configuration space to be restored at BMC reset. */
> > +struct ls2k_bmc_pci_data {
> > +     u32 pci_command;
> > +     u32 base_address0;
> > +     u32 interrupt_line;
> > +};
> > +
> > +/* Index of the parent PCI configuration space to be restored at BMC reset. */
> > +struct ls2k_bmc_bridge_pci_data {
> > +     u32 pci_command;
> > +     u32 base_address[6];
> > +     u32 rom_addreess;
> > +     u32 interrupt_line;
> > +     u32 msi_hi;
> > +     u32 msi_lo;
> > +     u32 devctl;
> > +     u32 linkcap;
> > +     u32 linkctl_sts;
> > +     u32 symbol_timer;
> > +     u32 gen2_ctrl;
> > +};
> > +
> > +struct ls2k_bmc_pdata {
>
> Drop the pdata part completely.
>
> pdata is something else.

Emm...
How about rename it as ls2k_bmc_priv? Otherwise, using ls2k_bmc as a
structure name seems a bit odd.

>
> > +     struct device *dev;
> > +     struct work_struct bmc_reset_work;
> > +     struct ls2k_bmc_pci_data bmc_pci_data;
> > +     struct ls2k_bmc_bridge_pci_data bridge_pci_data;
> > +};
> > +
> > +static bool ls2k_bmc_bar0_addr_is_set(struct pci_dev *pdev)
> > +{
> > +     u32 addr;
> > +
> > +     pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);
> > +
> > +     return addr & PCI_BASE_ADDRESS_MEM_MASK ? true : false;
> > +}
> > +
> > +static bool ls2k_bmc_pcie_is_connected(struct pci_dev *parent, struct ls2k_bmc_pdata *ddata)
> > +{
> > +     void __iomem *base;
> > +     int val, ret;
> > +
> > +     base = pci_iomap(parent, 0, LS7A_PCI_CFG_SIZE);
> > +     if (!base)
> > +             return false;
> > +
> > +     val = readl(base + LS7A_PCIE_PORT_CTL0);
> > +     writel(val | LS2K_BMC_PCIE_LTSSM_ENABLE, base + LS7A_PCIE_PORT_CTL0);
> > +
> > +     ret = readl_poll_timeout_atomic(base + LS7A_PCIE_PORT_STS1, val,
> > +                                     (val & LS2K_BMC_PCIE_LTSSM_STS) == LS2K_BMC_PCIE_CONNECTED,
> > +                                     LS2K_BMC_PCIE_DELAY_US, LS2K_BMC_PCIE_TIMEOUT_US);
> > +     if (ret) {
> > +             pci_iounmap(parent, base);
> > +             dev_err(ddata->dev, "PCI-E training failed status=0x%x\n", val);
> > +             return false;
> > +     }
> > +
> > +     pci_iounmap(parent, base);
> > +     return true;
> > +}
> > +
> > +static void ls2k_bmc_restore_bridge_pci_data(struct pci_dev *parent, struct ls2k_bmc_pdata *ddata)
> > +{
> > +     int base, i = 0;
> > +
> > +     pci_write_config_dword(parent, PCI_COMMAND, ddata->bridge_pci_data.pci_command);
> > +
> > +     for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += 4, i++)
>
> Define 4.
>
> > +             pci_write_config_dword(parent, base, ddata->bridge_pci_data.base_address[i]);
> > +
> > +     pci_write_config_dword(parent, PCI_ROM_ADDRESS, ddata->bridge_pci_data.rom_addreess);
> > +     pci_write_config_dword(parent, PCI_INTERRUPT_LINE, ddata->bridge_pci_data.interrupt_line);
> > +
> > +     pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO,
> > +                            ddata->bridge_pci_data.msi_lo);
> > +     pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI,
> > +                            ddata->bridge_pci_data.msi_hi);
> > +     pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL,
> > +                            ddata->bridge_pci_data.devctl);
> > +     pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP,
> > +                            ddata->bridge_pci_data.linkcap);
> > +     pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL,
> > +                            ddata->bridge_pci_data.linkctl_sts);
> > +
> > +     pci_write_config_dword(parent, LS7A_GEN2_CTL, ddata->bridge_pci_data.gen2_ctrl);
> > +     pci_write_config_dword(parent, LS7A_SYMBOL_TIMER, ddata->bridge_pci_data.symbol_timer);
> > +}
> > +
> > +static int ls2k_bmc_recover_pci_data(void *data)
> > +{
> > +     struct ls2k_bmc_pdata *ddata = data;
> > +     struct pci_dev *pdev = to_pci_dev(ddata->dev);
> > +     struct pci_dev *parent = pdev->bus->self;
> > +     u32 i;
> > +
> > +     /*
> > +      * Clear the bus, io and mem resources of the PCI-E bridge to zero, so that
> > +      * the processor can not access the LS2K PCI-E port, to avoid crashing due to
> > +      * the lack of return signal from accessing the LS2K PCI-E port.
> > +      */
> > +     pci_write_config_dword(parent, PCI_BASE_ADDRESS_2, 0);
> > +     pci_write_config_dword(parent, PCI_BASE_ADDRESS_3, 0);
> > +     pci_write_config_dword(parent, PCI_BASE_ADDRESS_4, 0);
> > +
> > +     /*
> > +      * When the LS2K BMC is reset, the LS7A PCI-E port is also reset, and its PCI
> > +      * BAR0 register is cleared. Due to the time gap between the GPIO interrupt
> > +      * generation and the LS2K BMC reset, the LS7A PCI BAR0 register is read to
> > +      * determine whether the reset has begun.
> > +      */
> > +     for (i = LS7A_BAR0_CHECK_MAX_TIMES; i > 0 ; i--) {
> > +             if (!ls2k_bmc_bar0_addr_is_set(parent))
> > +                     break;
> > +             mdelay(1);
> > +     };
> > +
> > +     if (i == 0)
> > +             return false;
> > +
> > +     ls2k_bmc_restore_bridge_pci_data(parent, ddata);
> > +
> > +     /* Check if PCI-E is connected */
> > +     if (!ls2k_bmc_pcie_is_connected(parent, ddata))
> > +             return false;
> > +
> > +     /* Waiting for U-Boot and DDR ready */
> > +     mdelay(LS2K_BMC_RESET_WAIT_TIME);
> > +     if (!ls2k_bmc_bar0_addr_is_set(parent))
> > +             return false;
> > +
> > +     /* Restore LS2K BMC PCI-E config data */
> > +     pci_write_config_dword(pdev, PCI_COMMAND, ddata->bmc_pci_data.pci_command);
> > +     pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, ddata->bmc_pci_data.base_address0);
> > +     pci_write_config_dword(pdev, PCI_INTERRUPT_LINE, ddata->bmc_pci_data.interrupt_line);
> > +
> > +     return 0;
> > +}
> > +
> > +static void ls2k_bmc_events_fn(struct work_struct *work)
> > +{
> > +     struct ls2k_bmc_pdata *ddata = container_of(work, struct ls2k_bmc_pdata, bmc_reset_work);
> > +
> > +     /*
> > +      * The PCI-E is lost when the BMC resets, at which point access to the PCI-E
> > +      * from other CPUs is suspended to prevent a crash.
> > +      */
> > +     stop_machine(ls2k_bmc_recover_pci_data, ddata, NULL);
> > +
> > +     if (IS_ENABLED(CONFIG_VT)) {
> > +             /* Re-push the display due to previous PCI-E loss. */
> > +             set_console(vt_move_to_console(MAX_NR_CONSOLES - 1, 1));
> > +     }
> > +}
> > +
> > +static irqreturn_t ls2k_bmc_interrupt(int irq, void *arg)
> > +{
> > +     struct ls2k_bmc_pdata *ddata = arg;
> > +     static unsigned long last_jiffies;
> > +
> > +     if (system_state != SYSTEM_RUNNING)
> > +             return IRQ_HANDLED;
> > +
> > +     /* Skip interrupt in LS2K_BMC_INT_INTERVAL */
> > +     if (time_after(jiffies, last_jiffies + LS2K_BMC_INT_INTERVAL)) {
> > +             schedule_work(&ddata->bmc_reset_work);
> > +             last_jiffies = jiffies;
> > +     }
> > +
> > +     return IRQ_HANDLED;
> > +}
> > +
> > +/*
> > + * Saves the BMC parent device (LS7A) and its own PCI configuration space registers
> > + * that need to be restored after BMC reset.
> > + */
> > +static void ls2k_bmc_save_pci_data(struct pci_dev *pdev, struct ls2k_bmc_pdata *ddata)
> > +{
> > +     struct pci_dev *parent = pdev->bus->self;
> > +     int base, i = 0;
> > +
> > +     pci_read_config_dword(parent, PCI_COMMAND, &ddata->bridge_pci_data.pci_command);
> > +
> > +     for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += 4, i++)
> > +             pci_read_config_dword(parent, base, &ddata->bridge_pci_data.base_address[i]);
> > +
> > +     pci_read_config_dword(parent, PCI_ROM_ADDRESS, &ddata->bridge_pci_data.rom_addreess);
> > +     pci_read_config_dword(parent, PCI_INTERRUPT_LINE, &ddata->bridge_pci_data.interrupt_line);
> > +
> > +     pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO,
> > +                           &ddata->bridge_pci_data.msi_lo);
> > +     pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI,
> > +                           &ddata->bridge_pci_data.msi_hi);
> > +
> > +     pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL,
> > +                           &ddata->bridge_pci_data.devctl);
> > +     pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP,
> > +                           &ddata->bridge_pci_data.linkcap);
> > +     pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL,
> > +                           &ddata->bridge_pci_data.linkctl_sts);
> > +
> > +     pci_read_config_dword(parent, LS7A_GEN2_CTL, &ddata->bridge_pci_data.gen2_ctrl);
> > +     ddata->bridge_pci_data.gen2_ctrl |= FIELD_PREP(LS7A_GEN2_SPEED_CHANG, 0x1)
> > +                                     | FIELD_PREP(LS7A_CONF_PHY_TX, 0x0);
> > +
> > +     pci_read_config_dword(parent, LS7A_SYMBOL_TIMER, &ddata->bridge_pci_data.symbol_timer);
> > +     ddata->bridge_pci_data.symbol_timer |= LS7A_MASK_LEN_MATCH;
> > +
> > +     pci_read_config_dword(pdev, PCI_COMMAND, &ddata->bmc_pci_data.pci_command);
> > +     pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &ddata->bmc_pci_data.base_address0);
> > +     pci_read_config_dword(pdev, PCI_INTERRUPT_LINE, &ddata->bmc_pci_data.interrupt_line);
> > +}
> > +
> > +static int ls2k_bmc_pdata_initial(struct ls2k_bmc_pdata *ddata)
>
> What are you actually doing here exactly.
>
> I don't think "pdata_initial" describes it.

Indeed, as the function expands, its name should be updated.
It now handles multiple tasks, such as GPIO initialization and
interrupt registration. Overall, it initializes the ls2k BMC device.

How about renaming it to ls2k_bmc_device_request()?
>
> > +{
> > +     struct pci_dev *pdev = to_pci_dev(ddata->dev);
> > +     int gsi = 16 + (LS2K_BMC_RESET_GPIO & 7);
>
> Define 16.
>
> > +     void __iomem *gpio_base;
> > +     int irq, ret, val;
> > +
> > +     ls2k_bmc_save_pci_data(pdev, ddata);
> > +
> > +     INIT_WORK(&ddata->bmc_reset_work, ls2k_bmc_events_fn);
> > +
> > +     ret = devm_request_irq(&pdev->dev, pdev->irq, ls2k_bmc_interrupt,
> > +                            IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc pcie", ddata);
> > +     if (ret) {
> > +             dev_err(ddata->dev, "Failed to request LS2KBMC PCI-E IRQ %d.\n", pdev->irq);
> > +             return ret;
> > +     }
> > +
> > +     /*
> > +      * Since gpio_chip->to_irq is not implemented in the Loongson-3 GPIO driver,
> > +      * acpi_register_gsi() is used to obtain the GPIO IRQ. The GPIO interrupt is a
> > +      * watchdog interrupt that is triggered when the BMC resets.
> > +      */
> > +     irq = acpi_register_gsi(NULL, gsi, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW);
> > +     if (irq < 0)
> > +             return irq;
> > +
> > +     gpio_base = ioremap(LOONGSON_GPIO_REG_BASE, LOONGSON_GPIO_REG_SIZE);
> > +     if (!gpio_base) {
> > +             ret = -ENOMEM;
> > +             goto acpi_failed;
> > +     }
> > +
> > +     /* Disable GPIO output */
> > +     val = readl(gpio_base + LOONGSON_GPIO_OEN);
> > +     writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_OEN);
> > +
> > +     /* Enable GPIO functionality */
> > +     val = readl(gpio_base + LOONGSON_GPIO_FUNC);
> > +     writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_FUNC);
> > +
> > +     /* Set GPIO interrupts to low-level active */
> > +     val = readl(gpio_base + LOONGSON_GPIO_INTPOL);
> > +     writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTPOL);
> > +
> > +     /* Enable GPIO interrupts */
> > +     val = readl(gpio_base + LOONGSON_GPIO_INTEN);
> > +     writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTEN);
> > +
> > +     ret = devm_request_irq(ddata->dev, irq, ls2k_bmc_interrupt,
> > +                            IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc gpio", ddata);
> > +     if (ret)
> > +             dev_err(ddata->dev, "Failed to request LS2KBMC GPIO IRQ %d.\n", irq);
> > +
> > +     iounmap(gpio_base);
> > +
> > +acpi_failed:
> > +     acpi_unregister_gsi(gsi);
> > +     return ret;
> > +}
> > +
> >  /*
> >   * Currently the Loongson-2K BMC hardware does not have an I2C interface to adapt to the
> >   * resolution. We set the resolution by presetting "video=1280x1024-16@2M" to the BMC memory.
> > @@ -134,6 +457,7 @@ static int ls2k_bmc_parse_mode(struct pci_dev *pdev, struct simplefb_platform_da
> >  static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
> >  {
> >       struct simplefb_platform_data pd;
> > +     struct ls2k_bmc_pdata *ddata;
> >       resource_size_t base;
> >       int ret;
> >
> > @@ -141,6 +465,18 @@ static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
> >       if (ret)
> >               return ret;
> >
> > +     ddata = devm_kzalloc(&dev->dev, sizeof(*ddata), GFP_KERNEL);
> > +     if (IS_ERR(ddata)) {
> > +             ret = -ENOMEM;
> > +             goto disable_pci;
> > +     }
> > +
> > +     ddata->dev = &dev->dev;
> > +
> > +     ret = ls2k_bmc_pdata_initial(ddata);
> > +     if (ret)
> > +             goto disable_pci;
> > +
> >       ret = ls2k_bmc_parse_mode(dev, &pd);
> >       if (ret)
> >               goto disable_pci;
> > --
> > 2.47.3
> >
>
> --
> Lee Jones [李琼斯]

--
Thanks.
Binbin

Re: [PATCH v10 2/3] mfd: ls2kbmc: Add Loongson-2K BMC reset function support

[Lee Jones]

On Wed, 03 Sep 2025, Binbin Zhou wrote:

> Hi Lee:
> 
> Thanks for your reply.
> 
> On Tue, Sep 2, 2025 at 10:46 PM Lee Jones <lee@kernel.org> wrote:
> >
> > On Fri, 22 Aug 2025, Binbin Zhou wrote:
> >
> > > Since the display is a sub-function of the Loongson-2K BMC, when the
> > > BMC reset, the entire BMC PCIe is disconnected, including the display
> > > which is interrupted.
> > >
> > > Quick overview of the entire LS2K BMC reset process:
> > >
> > > There are two types of reset methods: soft reset (BMC-initiated reboot
> > > of IPMI reset command) and BMC watchdog reset (watchdog timeout).
> > >
> > > First, regardless of the method, an interrupt is generated (PCIe interrupt
> > > for soft reset/GPIO interrupt for watchdog reset);
> > >
> > > Second, during the interrupt process, the system enters bmc_reset_work,
> > > clears the bus/IO/mem resources of the LS7A PCI-E bridge, waits for the BMC
> > > reset to begin, then restores the parent device's PCI configuration space,
> > > waits for the BMC reset to complete, and finally restores the BMC PCI
> > > configuration space.
> > >
> > > Display restoration occurs last.
> > >
> > > Co-developed-by: Chong Qiao <qiaochong@loongson.cn>
> > > Signed-off-by: Chong Qiao <qiaochong@loongson.cn>
> > > Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
> > > Acked-by: Corey Minyard <corey@minyard.net>
> > > Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
> > > ---
> > >  drivers/mfd/ls2k-bmc-core.c | 336 ++++++++++++++++++++++++++++++++++++
> > >  1 file changed, 336 insertions(+)
> >
> > Couple of nits to finish up:
> >
> > > diff --git a/drivers/mfd/ls2k-bmc-core.c b/drivers/mfd/ls2k-bmc-core.c
> > > index 39cc481d9ba1..fa7f1a822076 100644
> > > --- a/drivers/mfd/ls2k-bmc-core.c
> > > +++ b/drivers/mfd/ls2k-bmc-core.c
> > > @@ -10,8 +10,12 @@
> > >   */
> > >
> > >  #include <linux/aperture.h>
> > > +#include <linux/bitfield.h>
> > > +#include <linux/delay.h>
> > >  #include <linux/errno.h>
> > >  #include <linux/init.h>
> > > +#include <linux/iopoll.h>
> > > +#include <linux/kbd_kern.h>
> > >  #include <linux/kernel.h>
> > >  #include <linux/mfd/core.h>
> > >  #include <linux/module.h>
> > > @@ -19,6 +23,8 @@
> > >  #include <linux/pci_ids.h>
> > >  #include <linux/platform_data/simplefb.h>
> > >  #include <linux/platform_device.h>
> > > +#include <linux/stop_machine.h>
> > > +#include <linux/vt_kern.h>
> > >
> > >  /* LS2K BMC resources */
> > >  #define LS2K_DISPLAY_RES_START               (SZ_16M + SZ_2M)
> > > @@ -29,6 +35,48 @@
> > >  #define LS2K_IPMI3_RES_START         (LS2K_IPMI2_RES_START + LS2K_IPMI_RES_SIZE)
> > >  #define LS2K_IPMI4_RES_START         (LS2K_IPMI3_RES_START + LS2K_IPMI_RES_SIZE)
> > >
> > > +#define LS7A_PCI_CFG_SIZE            0x100
> > > +
> > > +/* LS7A bridge registers */
> > > +#define LS7A_PCIE_PORT_CTL0          0x0
> > > +#define LS7A_PCIE_PORT_STS1          0xC
> > > +#define LS7A_GEN2_CTL                        0x80C
> > > +#define LS7A_SYMBOL_TIMER            0x71C
> > > +
> > > +/* Bits of LS7A_PCIE_PORT_CTL0 */
> > > +#define LS2K_BMC_PCIE_LTSSM_ENABLE   BIT(3)
> > > +
> > > +/* Bits of LS7A_PCIE_PORT_STS1 */
> > > +#define LS2K_BMC_PCIE_LTSSM_STS              GENMASK(5, 0)
> > > +#define LS2K_BMC_PCIE_CONNECTED              0x11
> > > +
> > > +#define LS2K_BMC_PCIE_DELAY_US               1000
> > > +#define LS2K_BMC_PCIE_TIMEOUT_US     1000000
> > > +
> > > +/* Bits of LS7A_GEN2_CTL */
> > > +#define LS7A_GEN2_SPEED_CHANG                BIT(17)
> > > +#define LS7A_CONF_PHY_TX             BIT(18)
> > > +
> > > +/* Bits of LS7A_SYMBOL_TIMER */
> > > +#define LS7A_MASK_LEN_MATCH          BIT(26)
> > > +
> > > +/* Interval between interruptions */
> > > +#define LS2K_BMC_INT_INTERVAL                (60 * HZ)
> > > +
> > > +/* Maximum time to wait for U-Boot and DDR to be ready with ms. */
> > > +#define LS2K_BMC_RESET_WAIT_TIME     10000
> > > +
> > > +/* It's an experience value */
> > > +#define LS7A_BAR0_CHECK_MAX_TIMES    2000
> > > +
> > > +#define LS2K_BMC_RESET_GPIO          14
> > > +#define LOONGSON_GPIO_REG_BASE               0x1FE00500
> > > +#define LOONGSON_GPIO_REG_SIZE               0x18
> > > +#define LOONGSON_GPIO_OEN            0x0
> > > +#define LOONGSON_GPIO_FUNC           0x4
> > > +#define LOONGSON_GPIO_INTPOL         0x10
> > > +#define LOONGSON_GPIO_INTEN          0x14
> > > +
> > >  enum {
> > >       LS2K_BMC_DISPLAY,
> > >       LS2K_BMC_IPMI0,
> > > @@ -95,6 +143,281 @@ static struct mfd_cell ls2k_bmc_cells[] = {
> > >       },
> > >  };
> > >
> > > +/* Index of the BMC PCI configuration space to be restored at BMC reset. */
> > > +struct ls2k_bmc_pci_data {
> > > +     u32 pci_command;
> > > +     u32 base_address0;
> > > +     u32 interrupt_line;
> > > +};
> > > +
> > > +/* Index of the parent PCI configuration space to be restored at BMC reset. */
> > > +struct ls2k_bmc_bridge_pci_data {
> > > +     u32 pci_command;
> > > +     u32 base_address[6];
> > > +     u32 rom_addreess;
> > > +     u32 interrupt_line;
> > > +     u32 msi_hi;
> > > +     u32 msi_lo;
> > > +     u32 devctl;
> > > +     u32 linkcap;
> > > +     u32 linkctl_sts;
> > > +     u32 symbol_timer;
> > > +     u32 gen2_ctrl;
> > > +};
> > > +
> > > +struct ls2k_bmc_pdata {
> >
> > Drop the pdata part completely.
> >
> > pdata is something else.
> 
> Emm...
> How about rename it as ls2k_bmc_priv? Otherwise, using ls2k_bmc as a
> structure name seems a bit odd.

Either ls2k_bmc or ls2k_bmc_ddata would do.  Both are common
nomenclature choices and we know what both of them mean.

> > > +     struct device *dev;
> > > +     struct work_struct bmc_reset_work;
> > > +     struct ls2k_bmc_pci_data bmc_pci_data;
> > > +     struct ls2k_bmc_bridge_pci_data bridge_pci_data;
> > > +};
> > > +
> > > +static bool ls2k_bmc_bar0_addr_is_set(struct pci_dev *pdev)
> > > +{
> > > +     u32 addr;
> > > +
> > > +     pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &addr);
> > > +
> > > +     return addr & PCI_BASE_ADDRESS_MEM_MASK ? true : false;
> > > +}
> > > +
> > > +static bool ls2k_bmc_pcie_is_connected(struct pci_dev *parent, struct ls2k_bmc_pdata *ddata)
> > > +{
> > > +     void __iomem *base;
> > > +     int val, ret;
> > > +
> > > +     base = pci_iomap(parent, 0, LS7A_PCI_CFG_SIZE);
> > > +     if (!base)
> > > +             return false;
> > > +
> > > +     val = readl(base + LS7A_PCIE_PORT_CTL0);
> > > +     writel(val | LS2K_BMC_PCIE_LTSSM_ENABLE, base + LS7A_PCIE_PORT_CTL0);
> > > +
> > > +     ret = readl_poll_timeout_atomic(base + LS7A_PCIE_PORT_STS1, val,
> > > +                                     (val & LS2K_BMC_PCIE_LTSSM_STS) == LS2K_BMC_PCIE_CONNECTED,
> > > +                                     LS2K_BMC_PCIE_DELAY_US, LS2K_BMC_PCIE_TIMEOUT_US);
> > > +     if (ret) {
> > > +             pci_iounmap(parent, base);
> > > +             dev_err(ddata->dev, "PCI-E training failed status=0x%x\n", val);
> > > +             return false;
> > > +     }
> > > +
> > > +     pci_iounmap(parent, base);
> > > +     return true;
> > > +}
> > > +
> > > +static void ls2k_bmc_restore_bridge_pci_data(struct pci_dev *parent, struct ls2k_bmc_pdata *ddata)
> > > +{
> > > +     int base, i = 0;
> > > +
> > > +     pci_write_config_dword(parent, PCI_COMMAND, ddata->bridge_pci_data.pci_command);
> > > +
> > > +     for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += 4, i++)
> >
> > Define 4.
> >
> > > +             pci_write_config_dword(parent, base, ddata->bridge_pci_data.base_address[i]);
> > > +
> > > +     pci_write_config_dword(parent, PCI_ROM_ADDRESS, ddata->bridge_pci_data.rom_addreess);
> > > +     pci_write_config_dword(parent, PCI_INTERRUPT_LINE, ddata->bridge_pci_data.interrupt_line);
> > > +
> > > +     pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO,
> > > +                            ddata->bridge_pci_data.msi_lo);
> > > +     pci_write_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI,
> > > +                            ddata->bridge_pci_data.msi_hi);
> > > +     pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL,
> > > +                            ddata->bridge_pci_data.devctl);
> > > +     pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP,
> > > +                            ddata->bridge_pci_data.linkcap);
> > > +     pci_write_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL,
> > > +                            ddata->bridge_pci_data.linkctl_sts);
> > > +
> > > +     pci_write_config_dword(parent, LS7A_GEN2_CTL, ddata->bridge_pci_data.gen2_ctrl);
> > > +     pci_write_config_dword(parent, LS7A_SYMBOL_TIMER, ddata->bridge_pci_data.symbol_timer);
> > > +}
> > > +
> > > +static int ls2k_bmc_recover_pci_data(void *data)
> > > +{
> > > +     struct ls2k_bmc_pdata *ddata = data;
> > > +     struct pci_dev *pdev = to_pci_dev(ddata->dev);
> > > +     struct pci_dev *parent = pdev->bus->self;
> > > +     u32 i;
> > > +
> > > +     /*
> > > +      * Clear the bus, io and mem resources of the PCI-E bridge to zero, so that
> > > +      * the processor can not access the LS2K PCI-E port, to avoid crashing due to
> > > +      * the lack of return signal from accessing the LS2K PCI-E port.
> > > +      */
> > > +     pci_write_config_dword(parent, PCI_BASE_ADDRESS_2, 0);
> > > +     pci_write_config_dword(parent, PCI_BASE_ADDRESS_3, 0);
> > > +     pci_write_config_dword(parent, PCI_BASE_ADDRESS_4, 0);
> > > +
> > > +     /*
> > > +      * When the LS2K BMC is reset, the LS7A PCI-E port is also reset, and its PCI
> > > +      * BAR0 register is cleared. Due to the time gap between the GPIO interrupt
> > > +      * generation and the LS2K BMC reset, the LS7A PCI BAR0 register is read to
> > > +      * determine whether the reset has begun.
> > > +      */
> > > +     for (i = LS7A_BAR0_CHECK_MAX_TIMES; i > 0 ; i--) {
> > > +             if (!ls2k_bmc_bar0_addr_is_set(parent))
> > > +                     break;
> > > +             mdelay(1);
> > > +     };
> > > +
> > > +     if (i == 0)
> > > +             return false;
> > > +
> > > +     ls2k_bmc_restore_bridge_pci_data(parent, ddata);
> > > +
> > > +     /* Check if PCI-E is connected */
> > > +     if (!ls2k_bmc_pcie_is_connected(parent, ddata))
> > > +             return false;
> > > +
> > > +     /* Waiting for U-Boot and DDR ready */
> > > +     mdelay(LS2K_BMC_RESET_WAIT_TIME);
> > > +     if (!ls2k_bmc_bar0_addr_is_set(parent))
> > > +             return false;
> > > +
> > > +     /* Restore LS2K BMC PCI-E config data */
> > > +     pci_write_config_dword(pdev, PCI_COMMAND, ddata->bmc_pci_data.pci_command);
> > > +     pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, ddata->bmc_pci_data.base_address0);
> > > +     pci_write_config_dword(pdev, PCI_INTERRUPT_LINE, ddata->bmc_pci_data.interrupt_line);
> > > +
> > > +     return 0;
> > > +}
> > > +
> > > +static void ls2k_bmc_events_fn(struct work_struct *work)
> > > +{
> > > +     struct ls2k_bmc_pdata *ddata = container_of(work, struct ls2k_bmc_pdata, bmc_reset_work);
> > > +
> > > +     /*
> > > +      * The PCI-E is lost when the BMC resets, at which point access to the PCI-E
> > > +      * from other CPUs is suspended to prevent a crash.
> > > +      */
> > > +     stop_machine(ls2k_bmc_recover_pci_data, ddata, NULL);
> > > +
> > > +     if (IS_ENABLED(CONFIG_VT)) {
> > > +             /* Re-push the display due to previous PCI-E loss. */
> > > +             set_console(vt_move_to_console(MAX_NR_CONSOLES - 1, 1));
> > > +     }
> > > +}
> > > +
> > > +static irqreturn_t ls2k_bmc_interrupt(int irq, void *arg)
> > > +{
> > > +     struct ls2k_bmc_pdata *ddata = arg;
> > > +     static unsigned long last_jiffies;
> > > +
> > > +     if (system_state != SYSTEM_RUNNING)
> > > +             return IRQ_HANDLED;
> > > +
> > > +     /* Skip interrupt in LS2K_BMC_INT_INTERVAL */
> > > +     if (time_after(jiffies, last_jiffies + LS2K_BMC_INT_INTERVAL)) {
> > > +             schedule_work(&ddata->bmc_reset_work);
> > > +             last_jiffies = jiffies;
> > > +     }
> > > +
> > > +     return IRQ_HANDLED;
> > > +}
> > > +
> > > +/*
> > > + * Saves the BMC parent device (LS7A) and its own PCI configuration space registers
> > > + * that need to be restored after BMC reset.
> > > + */
> > > +static void ls2k_bmc_save_pci_data(struct pci_dev *pdev, struct ls2k_bmc_pdata *ddata)
> > > +{
> > > +     struct pci_dev *parent = pdev->bus->self;
> > > +     int base, i = 0;
> > > +
> > > +     pci_read_config_dword(parent, PCI_COMMAND, &ddata->bridge_pci_data.pci_command);
> > > +
> > > +     for (base = PCI_BASE_ADDRESS_0; base <= PCI_BASE_ADDRESS_5; base += 4, i++)
> > > +             pci_read_config_dword(parent, base, &ddata->bridge_pci_data.base_address[i]);
> > > +
> > > +     pci_read_config_dword(parent, PCI_ROM_ADDRESS, &ddata->bridge_pci_data.rom_addreess);
> > > +     pci_read_config_dword(parent, PCI_INTERRUPT_LINE, &ddata->bridge_pci_data.interrupt_line);
> > > +
> > > +     pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_LO,
> > > +                           &ddata->bridge_pci_data.msi_lo);
> > > +     pci_read_config_dword(parent, parent->msi_cap + PCI_MSI_ADDRESS_HI,
> > > +                           &ddata->bridge_pci_data.msi_hi);
> > > +
> > > +     pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_DEVCTL,
> > > +                           &ddata->bridge_pci_data.devctl);
> > > +     pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCAP,
> > > +                           &ddata->bridge_pci_data.linkcap);
> > > +     pci_read_config_dword(parent, parent->pcie_cap + PCI_EXP_LNKCTL,
> > > +                           &ddata->bridge_pci_data.linkctl_sts);
> > > +
> > > +     pci_read_config_dword(parent, LS7A_GEN2_CTL, &ddata->bridge_pci_data.gen2_ctrl);
> > > +     ddata->bridge_pci_data.gen2_ctrl |= FIELD_PREP(LS7A_GEN2_SPEED_CHANG, 0x1)
> > > +                                     | FIELD_PREP(LS7A_CONF_PHY_TX, 0x0);
> > > +
> > > +     pci_read_config_dword(parent, LS7A_SYMBOL_TIMER, &ddata->bridge_pci_data.symbol_timer);
> > > +     ddata->bridge_pci_data.symbol_timer |= LS7A_MASK_LEN_MATCH;
> > > +
> > > +     pci_read_config_dword(pdev, PCI_COMMAND, &ddata->bmc_pci_data.pci_command);
> > > +     pci_read_config_dword(pdev, PCI_BASE_ADDRESS_0, &ddata->bmc_pci_data.base_address0);
> > > +     pci_read_config_dword(pdev, PCI_INTERRUPT_LINE, &ddata->bmc_pci_data.interrupt_line);
> > > +}
> > > +
> > > +static int ls2k_bmc_pdata_initial(struct ls2k_bmc_pdata *ddata)
> >
> > What are you actually doing here exactly.
> >
> > I don't think "pdata_initial" describes it.
> 
> Indeed, as the function expands, its name should be updated.
> It now handles multiple tasks, such as GPIO initialization and
> interrupt registration. Overall, it initializes the ls2k BMC device.
> 
> How about renaming it to ls2k_bmc_device_request()?

ls2k_bmc_init() is common.

> > > +{
> > > +     struct pci_dev *pdev = to_pci_dev(ddata->dev);
> > > +     int gsi = 16 + (LS2K_BMC_RESET_GPIO & 7);
> >
> > Define 16.
> >
> > > +     void __iomem *gpio_base;
> > > +     int irq, ret, val;
> > > +
> > > +     ls2k_bmc_save_pci_data(pdev, ddata);
> > > +
> > > +     INIT_WORK(&ddata->bmc_reset_work, ls2k_bmc_events_fn);
> > > +
> > > +     ret = devm_request_irq(&pdev->dev, pdev->irq, ls2k_bmc_interrupt,
> > > +                            IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc pcie", ddata);
> > > +     if (ret) {
> > > +             dev_err(ddata->dev, "Failed to request LS2KBMC PCI-E IRQ %d.\n", pdev->irq);
> > > +             return ret;
> > > +     }
> > > +
> > > +     /*
> > > +      * Since gpio_chip->to_irq is not implemented in the Loongson-3 GPIO driver,
> > > +      * acpi_register_gsi() is used to obtain the GPIO IRQ. The GPIO interrupt is a
> > > +      * watchdog interrupt that is triggered when the BMC resets.
> > > +      */
> > > +     irq = acpi_register_gsi(NULL, gsi, ACPI_EDGE_SENSITIVE, ACPI_ACTIVE_LOW);
> > > +     if (irq < 0)
> > > +             return irq;
> > > +
> > > +     gpio_base = ioremap(LOONGSON_GPIO_REG_BASE, LOONGSON_GPIO_REG_SIZE);
> > > +     if (!gpio_base) {
> > > +             ret = -ENOMEM;
> > > +             goto acpi_failed;
> > > +     }
> > > +
> > > +     /* Disable GPIO output */
> > > +     val = readl(gpio_base + LOONGSON_GPIO_OEN);
> > > +     writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_OEN);
> > > +
> > > +     /* Enable GPIO functionality */
> > > +     val = readl(gpio_base + LOONGSON_GPIO_FUNC);
> > > +     writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_FUNC);
> > > +
> > > +     /* Set GPIO interrupts to low-level active */
> > > +     val = readl(gpio_base + LOONGSON_GPIO_INTPOL);
> > > +     writel(val & ~BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTPOL);
> > > +
> > > +     /* Enable GPIO interrupts */
> > > +     val = readl(gpio_base + LOONGSON_GPIO_INTEN);
> > > +     writel(val | BIT(LS2K_BMC_RESET_GPIO), gpio_base + LOONGSON_GPIO_INTEN);
> > > +
> > > +     ret = devm_request_irq(ddata->dev, irq, ls2k_bmc_interrupt,
> > > +                            IRQF_SHARED | IRQF_TRIGGER_FALLING, "ls2kbmc gpio", ddata);
> > > +     if (ret)
> > > +             dev_err(ddata->dev, "Failed to request LS2KBMC GPIO IRQ %d.\n", irq);
> > > +
> > > +     iounmap(gpio_base);
> > > +
> > > +acpi_failed:
> > > +     acpi_unregister_gsi(gsi);
> > > +     return ret;
> > > +}
> > > +
> > >  /*
> > >   * Currently the Loongson-2K BMC hardware does not have an I2C interface to adapt to the
> > >   * resolution. We set the resolution by presetting "video=1280x1024-16@2M" to the BMC memory.
> > > @@ -134,6 +457,7 @@ static int ls2k_bmc_parse_mode(struct pci_dev *pdev, struct simplefb_platform_da
> > >  static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
> > >  {
> > >       struct simplefb_platform_data pd;
> > > +     struct ls2k_bmc_pdata *ddata;
> > >       resource_size_t base;
> > >       int ret;
> > >
> > > @@ -141,6 +465,18 @@ static int ls2k_bmc_probe(struct pci_dev *dev, const struct pci_device_id *id)
> > >       if (ret)
> > >               return ret;
> > >
> > > +     ddata = devm_kzalloc(&dev->dev, sizeof(*ddata), GFP_KERNEL);
> > > +     if (IS_ERR(ddata)) {
> > > +             ret = -ENOMEM;
> > > +             goto disable_pci;
> > > +     }
> > > +
> > > +     ddata->dev = &dev->dev;
> > > +
> > > +     ret = ls2k_bmc_pdata_initial(ddata);
> > > +     if (ret)
> > > +             goto disable_pci;
> > > +
> > >       ret = ls2k_bmc_parse_mode(dev, &pd);
> > >       if (ret)
> > >               goto disable_pci;
> > > --
> > > 2.47.3
> > >
> >
> > --
> > Lee Jones [李琼斯]
> 
> --
> Thanks.
> Binbin

-- 
Lee Jones [李琼斯]

[PATCH v10 3/3] ipmi: Add Loongson-2K BMC support

[Binbin Zhou]

This patch adds Loongson-2K BMC IPMI support.

According to the existing design, we use software simulation to
implement the KCS interface registers: Stauts/Command/Data_Out/Data_In.

Also since both host side and BMC side read and write kcs status, fifo flag
is used to ensure data consistency.

The single KCS message block is as follows:

+-------------------------------------------------------------------------+
|FIFO flags| KCS register data | CMD data | KCS version | WR REQ | WR ACK |
+-------------------------------------------------------------------------+

Co-developed-by: Chong Qiao <qiaochong@loongson.cn>
Signed-off-by: Chong Qiao <qiaochong@loongson.cn>
Reviewed-by: Huacai Chen <chenhuacai@loongson.cn>
Acked-by: Corey Minyard <corey@minyard.net>
Signed-off-by: Binbin Zhou <zhoubinbin@loongson.cn>
---
 MAINTAINERS                      |   1 +
 drivers/char/ipmi/Kconfig        |   7 ++
 drivers/char/ipmi/Makefile       |   1 +
 drivers/char/ipmi/ipmi_si.h      |   7 ++
 drivers/char/ipmi/ipmi_si_intf.c |   4 +
 drivers/char/ipmi/ipmi_si_ls2k.c | 189 +++++++++++++++++++++++++++++++
 6 files changed, 209 insertions(+)
 create mode 100644 drivers/char/ipmi/ipmi_si_ls2k.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 48783add7a8b..560b76d00a30 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -14412,6 +14412,7 @@ LOONGSON-2K Board Management Controller (BMC) DRIVER
 M:	Binbin Zhou <zhoubinbin@loongson.cn>
 M:	Chong Qiao <qiaochong@loongson.cn>
 S:	Maintained
+F:	drivers/char/ipmi/ipmi_si_ls2k.c
 F:	drivers/mfd/ls2k-bmc-core.c
 
 LOONGSON EDAC DRIVER
diff --git a/drivers/char/ipmi/Kconfig b/drivers/char/ipmi/Kconfig
index f4adc6feb3b2..92bed266d07c 100644
--- a/drivers/char/ipmi/Kconfig
+++ b/drivers/char/ipmi/Kconfig
@@ -84,6 +84,13 @@ config IPMI_IPMB
 	  bus, and it also supports direct messaging on the bus using
 	  IPMB direct messages.  This module requires I2C support.
 
+config IPMI_LS2K
+	bool 'Loongson-2K IPMI interface'
+	depends on LOONGARCH
+	select MFD_LS2K_BMC_CORE
+	help
+	  Provides a driver for Loongson-2K IPMI interfaces.
+
 config IPMI_POWERNV
 	depends on PPC_POWERNV
 	tristate 'POWERNV (OPAL firmware) IPMI interface'
diff --git a/drivers/char/ipmi/Makefile b/drivers/char/ipmi/Makefile
index e0944547c9d0..4ea450a82242 100644
--- a/drivers/char/ipmi/Makefile
+++ b/drivers/char/ipmi/Makefile
@@ -8,6 +8,7 @@ ipmi_si-y := ipmi_si_intf.o ipmi_kcs_sm.o ipmi_smic_sm.o ipmi_bt_sm.o \
 	ipmi_si_mem_io.o
 ipmi_si-$(CONFIG_HAS_IOPORT) += ipmi_si_port_io.o
 ipmi_si-$(CONFIG_PCI) += ipmi_si_pci.o
+ipmi_si-$(CONFIG_IPMI_LS2K) += ipmi_si_ls2k.o
 ipmi_si-$(CONFIG_PARISC) += ipmi_si_parisc.o
 
 obj-$(CONFIG_IPMI_HANDLER) += ipmi_msghandler.o
diff --git a/drivers/char/ipmi/ipmi_si.h b/drivers/char/ipmi/ipmi_si.h
index 508c3fd45877..687835b53da5 100644
--- a/drivers/char/ipmi/ipmi_si.h
+++ b/drivers/char/ipmi/ipmi_si.h
@@ -101,6 +101,13 @@ void ipmi_si_pci_shutdown(void);
 static inline void ipmi_si_pci_init(void) { }
 static inline void ipmi_si_pci_shutdown(void) { }
 #endif
+#ifdef CONFIG_IPMI_LS2K
+void ipmi_si_ls2k_init(void);
+void ipmi_si_ls2k_shutdown(void);
+#else
+static inline void ipmi_si_ls2k_init(void) { }
+static inline void ipmi_si_ls2k_shutdown(void) { }
+#endif
 #ifdef CONFIG_PARISC
 void ipmi_si_parisc_init(void);
 void ipmi_si_parisc_shutdown(void);
diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c
index 8b5524069c15..cc7033e7f550 100644
--- a/drivers/char/ipmi/ipmi_si_intf.c
+++ b/drivers/char/ipmi/ipmi_si_intf.c
@@ -2120,6 +2120,8 @@ static int __init init_ipmi_si(void)
 
 	ipmi_si_pci_init();
 
+	ipmi_si_ls2k_init();
+
 	ipmi_si_parisc_init();
 
 	mutex_lock(&smi_infos_lock);
@@ -2331,6 +2333,8 @@ static void cleanup_ipmi_si(void)
 
 	ipmi_si_pci_shutdown();
 
+	ipmi_si_ls2k_shutdown();
+
 	ipmi_si_parisc_shutdown();
 
 	ipmi_si_platform_shutdown();
diff --git a/drivers/char/ipmi/ipmi_si_ls2k.c b/drivers/char/ipmi/ipmi_si_ls2k.c
new file mode 100644
index 000000000000..45442c257efd
--- /dev/null
+++ b/drivers/char/ipmi/ipmi_si_ls2k.c
@@ -0,0 +1,189 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Driver for Loongson-2K BMC IPMI interface
+ *
+ * Copyright (C) 2024-2025 Loongson Technology Corporation Limited.
+ *
+ * Authors:
+ *	Chong Qiao <qiaochong@loongson.cn>
+ *	Binbin Zhou <zhoubinbin@loongson.cn>
+ */
+
+#include <linux/bitfield.h>
+#include <linux/ioport.h>
+#include <linux/module.h>
+#include <linux/types.h>
+
+#include "ipmi_si.h"
+
+#define LS2K_KCS_FIFO_IBFH	0x0
+#define LS2K_KCS_FIFO_IBFT	0x1
+#define LS2K_KCS_FIFO_OBFH	0x2
+#define LS2K_KCS_FIFO_OBFT	0x3
+
+/* KCS registers */
+#define LS2K_KCS_REG_STS	0x4
+#define LS2K_KCS_REG_DATA_OUT	0x5
+#define LS2K_KCS_REG_DATA_IN	0x6
+#define LS2K_KCS_REG_CMD	0x8
+
+#define LS2K_KCS_CMD_DATA	0xa
+#define LS2K_KCS_VERSION	0xb
+#define LS2K_KCS_WR_REQ		0xc
+#define LS2K_KCS_WR_ACK		0x10
+
+#define LS2K_KCS_STS_OBF	BIT(0)
+#define LS2K_KCS_STS_IBF	BIT(1)
+#define LS2K_KCS_STS_SMS_ATN	BIT(2)
+#define LS2K_KCS_STS_CMD	BIT(3)
+
+#define LS2K_KCS_DATA_MASK	(LS2K_KCS_STS_OBF | LS2K_KCS_STS_IBF | LS2K_KCS_STS_CMD)
+
+static bool ls2k_registered;
+
+static unsigned char ls2k_mem_inb_v0(const struct si_sm_io *io, unsigned int offset)
+{
+	void __iomem *addr = io->addr;
+	int reg_offset;
+
+	if (offset & BIT(0)) {
+		reg_offset = LS2K_KCS_REG_STS;
+	} else {
+		writeb(readb(addr + LS2K_KCS_REG_STS) & ~LS2K_KCS_STS_OBF, addr + LS2K_KCS_REG_STS);
+		reg_offset = LS2K_KCS_REG_DATA_OUT;
+	}
+
+	return readb(addr + reg_offset);
+}
+
+static unsigned char ls2k_mem_inb_v1(const struct si_sm_io *io, unsigned int offset)
+{
+	void __iomem *addr = io->addr;
+	unsigned char inb = 0, cmd;
+	bool obf, ibf;
+
+	obf = readb(addr + LS2K_KCS_FIFO_OBFH) ^ readb(addr + LS2K_KCS_FIFO_OBFT);
+	ibf = readb(addr + LS2K_KCS_FIFO_IBFH) ^ readb(addr + LS2K_KCS_FIFO_IBFT);
+	cmd = readb(addr + LS2K_KCS_CMD_DATA);
+
+	if (offset & BIT(0)) {
+		inb = readb(addr + LS2K_KCS_REG_STS) & ~LS2K_KCS_DATA_MASK;
+		inb |= FIELD_PREP(LS2K_KCS_STS_OBF, obf)
+		    | FIELD_PREP(LS2K_KCS_STS_IBF, ibf)
+		    | FIELD_PREP(LS2K_KCS_STS_CMD, cmd);
+	} else {
+		inb = readb(addr + LS2K_KCS_REG_DATA_OUT);
+		writeb(readb(addr + LS2K_KCS_FIFO_OBFH), addr + LS2K_KCS_FIFO_OBFT);
+	}
+
+	return inb;
+}
+
+static void ls2k_mem_outb_v0(const struct si_sm_io *io, unsigned int offset,
+			     unsigned char val)
+{
+	void __iomem *addr = io->addr;
+	unsigned char sts = readb(addr + LS2K_KCS_REG_STS);
+	int reg_offset;
+
+	if (sts & LS2K_KCS_STS_IBF)
+		return;
+
+	if (offset & BIT(0)) {
+		reg_offset = LS2K_KCS_REG_CMD;
+		sts |= LS2K_KCS_STS_CMD;
+	} else {
+		reg_offset = LS2K_KCS_REG_DATA_IN;
+		sts &= ~LS2K_KCS_STS_CMD;
+	}
+
+	writew(val, addr + reg_offset);
+	writeb(sts | LS2K_KCS_STS_IBF, addr + LS2K_KCS_REG_STS);
+	writel(readl(addr + LS2K_KCS_WR_REQ) + 1, addr + LS2K_KCS_WR_REQ);
+}
+
+static void ls2k_mem_outb_v1(const struct si_sm_io *io, unsigned int offset,
+			     unsigned char val)
+{
+	void __iomem *addr = io->addr;
+	unsigned char ibfh, ibft;
+	int reg_offset;
+
+	ibfh = readb(addr + LS2K_KCS_FIFO_IBFH);
+	ibft = readb(addr + LS2K_KCS_FIFO_IBFT);
+
+	if (ibfh ^ ibft)
+		return;
+
+	reg_offset = (offset & BIT(0)) ? LS2K_KCS_REG_CMD : LS2K_KCS_REG_DATA_IN;
+	writew(val, addr + reg_offset);
+
+	writeb(offset & BIT(0), addr + LS2K_KCS_CMD_DATA);
+	writeb(!ibft, addr + LS2K_KCS_FIFO_IBFH);
+	writel(readl(addr + LS2K_KCS_WR_REQ) + 1, addr + LS2K_KCS_WR_REQ);
+}
+
+static void ls2k_mem_cleanup(struct si_sm_io *io)
+{
+	if (io->addr)
+		iounmap(io->addr);
+}
+
+static int ipmi_ls2k_mem_setup(struct si_sm_io *io)
+{
+	unsigned char version;
+
+	io->addr = ioremap(io->addr_data, io->regspacing);
+	if (!io->addr)
+		return -EIO;
+
+	version = readb(io->addr + LS2K_KCS_VERSION);
+
+	io->inputb = version ? ls2k_mem_inb_v1 : ls2k_mem_inb_v0;
+	io->outputb = version ? ls2k_mem_outb_v1 : ls2k_mem_outb_v0;
+	io->io_cleanup = ls2k_mem_cleanup;
+
+	return 0;
+}
+
+static int ipmi_ls2k_probe(struct platform_device *pdev)
+{
+	struct si_sm_io io;
+
+	memset(&io, 0, sizeof(io));
+
+	io.si_info	= &ipmi_kcs_si_info;
+	io.io_setup	= ipmi_ls2k_mem_setup;
+	io.addr_data	= pdev->resource[0].start;
+	io.regspacing	= resource_size(&pdev->resource[0]);
+	io.dev		= &pdev->dev;
+
+	dev_dbg(&pdev->dev, "addr 0x%lx, spacing %d.\n", io.addr_data, io.regspacing);
+
+	return ipmi_si_add_smi(&io);
+}
+
+static void ipmi_ls2k_remove(struct platform_device *pdev)
+{
+	ipmi_si_remove_by_dev(&pdev->dev);
+}
+
+struct platform_driver ipmi_ls2k_platform_driver = {
+	.driver = {
+		.name = "ls2k-ipmi-si",
+	},
+	.probe	= ipmi_ls2k_probe,
+	.remove	= ipmi_ls2k_remove,
+};
+
+void ipmi_si_ls2k_init(void)
+{
+	platform_driver_register(&ipmi_ls2k_platform_driver);
+	ls2k_registered = true;
+}
+
+void ipmi_si_ls2k_shutdown(void)
+{
+	if (ls2k_registered)
+		platform_driver_unregister(&ipmi_ls2k_platform_driver);
+}
-- 
2.47.3