[PATCH v2 0/4] Initial support for CTCISZ Forever Pi

[PATCH v2 0/4] Initial support for CTCISZ Forever Pi

[Yao Zi]

This series adds support for CTCISZ Forever Pi, which ships an Loongson
2K0300 SoC and various peripherals. The vendor prefix and the board are
documented and basic SoC/board devicetrees are added.

I've successfully booted into console with vendor U-Boot, a bootlog
could be obtained here[1]. DTB and initramfs must be built into the
kernel as the vendor bootloader cannot pass them and upstream U-Boot
support for LoongArch is still WIP.

Thanks for your time and review.

[1]: https://gist.github.com/ziyao233/54ef900406876b5554f627d1ba0e130e

Changed from v1 ("Initial support for CTCISZ Ninenine Pi")
- Board binding:
  - Use "Forever Pi" instead of "Ninenine Pi" as translation of the
    board model
- SoC devicetree:
  - Move UART aliases to the board dt
  - Add the missing space in definition of liointc0
- Link to v1: https://lore.kernel.org/all/20250501044239.9404-2-ziyao@disroot.org/

Yao Zi (4):
  dt-bindings: vendor-prefixes: Add CTCISZ Technology Co., LTD.
  dt-bindings: LoongArch: Add CTCISZ Forever Pi
  LoongArch: dts: Add initial SoC devicetree for Loongson 2K0300
  LoongArch: dts: Add initial devicetree for CTCISZ Forever Pi

 .../bindings/loongarch/loongson.yaml          |   5 +
 .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
 arch/loongarch/boot/dts/Makefile              |   1 +
 arch/loongarch/boot/dts/loongson-2k0300.dtsi  | 184 ++++++++++++++++++
 .../boot/dts/ls2k0300-ctcisz-forever-pi.dts   |  45 +++++
 5 files changed, 237 insertions(+)
 create mode 100644 arch/loongarch/boot/dts/loongson-2k0300.dtsi
 create mode 100644 arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts

-- 
2.49.0

[PATCH v2 1/4] dt-bindings: vendor-prefixes: Add CTCISZ Technology Co., LTD.

[Yao Zi]

CTCISZ Technology Co., LTD. is a company specializing in designing of
embedded systems. Document the vendor prefix.

Link: http://www.ctcisz.com/
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml
index 86f6a19b28ae..02f35e583948 100644
--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
+++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
@@ -344,6 +344,8 @@ patternProperties:
     description: Guangzhou China Star Optoelectronics Technology Co., Ltd
   "^csq,.*":
     description: Shenzen Chuangsiqi Technology Co.,Ltd.
+  "^ctcisz,.*":
+    description: CTCISZ Technology Co.,Ltd.
   "^ctera,.*":
     description: CTERA Networks Intl.
   "^ctu,.*":
-- 
2.49.0

[PATCH v2 2/4] dt-bindings: LoongArch: Add CTCISZ Forever Pi

[Yao Zi]

Forever Pi is an Loongson 2K0300-based development board produced by
CTCISZ. Features include,

- 512MiB DDR4 RAM
- On-board eMMC storage
- Optional SD Card support
- 2 USB 2.0 Ports (OTG and HOST)
- 1 GbE Ethernet port
- Optional WiFi/BT support
- Audio output through 3.5mm phone connector
- Optional display output through RAW RGB interface

Add compatible string for the board.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 Documentation/devicetree/bindings/loongarch/loongson.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/loongarch/loongson.yaml b/Documentation/devicetree/bindings/loongarch/loongson.yaml
index e1a4a97b7576..2479174ed454 100644
--- a/Documentation/devicetree/bindings/loongarch/loongson.yaml
+++ b/Documentation/devicetree/bindings/loongarch/loongson.yaml
@@ -14,6 +14,11 @@ properties:
     const: '/'
   compatible:
     oneOf:
+      - description: CTCISZ Forever Pi
+        items:
+          - const: ctcisz,forever-pi
+          - const: loongson,ls2k0300
+
       - description: Loongson-2K0500 processor based boards
         items:
           - const: loongson,ls2k0500-ref
-- 
2.49.0

[PATCH v2 3/4] LoongArch: dts: Add initial SoC devicetree for Loongson 2K0300

[Yao Zi]

Add SoC devicetree for 2K0300 SoC, which features one LA264 dual-issue
core and targets embedded market. Only CPU core, legacy interrupt
controllers and UARTs are defined for now.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/loongarch/boot/dts/loongson-2k0300.dtsi | 184 +++++++++++++++++++
 1 file changed, 184 insertions(+)
 create mode 100644 arch/loongarch/boot/dts/loongson-2k0300.dtsi

diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
new file mode 100644
index 000000000000..17974f793947
--- /dev/null
+++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
@@ -0,0 +1,184 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Loongson Technology Corporation Limited
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+/ {
+	compatible = "loongson,ls2k0300";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "loongson,la264";
+			reg = <0>;
+			device_type = "cpu";
+			clocks = <&cpu_clk>;
+		};
+
+	};
+
+	cpuintc: interrupt-controller {
+		compatible = "loongson,cpu-interrupt-controller";
+		interrupt-controller;
+		#interrupt-cells = <1>;
+	};
+
+	cpu_clk: clock-1000m {
+		compatible = "fixed-clock";
+		clock-frequency = <1000000000>;
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges = <0x00 0x10000000 0x00 0x10000000 0x0 0x10000000>,
+			 <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>,
+			 <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>;
+
+		liointc0: interrupt-controller@16001400 {
+			compatible = "loongson,liointc-2.0";
+			reg = <0x0 0x16001400 0x0 0x40>,
+			      <0x0 0x16001040 0x0 0x8>;
+			reg-names = "main", "isr0";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <2>;
+			interrupt-names = "int0";
+
+			loongson,parent_int_map = <0xffffffff>, /* int0 */
+						  <0x00000000>, /* int1 */
+						  <0x00000000>, /* int2 */
+						  <0x00000000>; /* int3 */
+		};
+
+		liointc1: interrupt-controller@16001440 {
+			compatible = "loongson,liointc-2.0";
+			reg = <0x0 0x16001440 0x0 0x40>,
+			      <0x0 0x16001048 0x0 0x8>;
+			reg-names = "main", "isr0";
+
+			interrupt-controller;
+			#interrupt-cells = <2>;
+
+			interrupt-parent = <&cpuintc>;
+			interrupts = <4>;
+			interrupt-names = "int2";
+
+			loongson,parent_int_map = <0x00000000>, /* int0 */
+						  <0x00000000>, /* int1 */
+						  <0xffffffff>, /* int2 */
+						  <0x00000000>; /* int3 */
+		};
+
+		uart0: serial@16100000 {
+			compatible = "ns16550a";
+			reg = <0 0x16100000 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart1: serial@16100400 {
+			compatible = "ns16550a";
+			reg = <0 0x16100400 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart2: serial@16100800 {
+			compatible = "ns16550a";
+			reg = <0 0x16100800 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart3: serial@16100c00 {
+			compatible = "ns16550a";
+			reg = <0 0x16100c00 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart4: serial@16101000 {
+			compatible = "ns16550a";
+			reg = <0 0x16101000 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart5: serial@16101400 {
+			compatible = "ns16550a";
+			reg = <0 0x16101400 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart6: serial@16101800 {
+			compatible = "ns16550a";
+			reg = <0 0x16101800 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart7: serial@16101c00 {
+			compatible = "ns16550a";
+			reg = <0 0x16101c00 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart8: serial@16102000 {
+			compatible = "ns16550a";
+			reg = <0 0x16102000 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		uart9: serial@16102400 {
+			compatible = "ns16550a";
+			reg = <0 0x16102400 0 0x10>;
+			interrupt-parent = <&liointc0>;
+			interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
+			no-loopback-test;
+			status = "disabled";
+		};
+
+		isa@16400000 {
+			compatible = "isa";
+			#address-cells = <2>;
+			#size-cells = <1>;
+			ranges = <1 0x0 0x0 0x16400000 0x4000>;
+		};
+	};
+};
-- 
2.49.0

[PATCH v2 4/4] LoongArch: dts: Add initial devicetree for CTCISZ Forever Pi

[Yao Zi]

Enable UART0 as it's the boot UART used by firmware.

Signed-off-by: Yao Zi <ziyao@disroot.org>
---
 arch/loongarch/boot/dts/Makefile              |  1 +
 .../boot/dts/ls2k0300-ctcisz-forever-pi.dts   | 45 +++++++++++++++++++
 2 files changed, 46 insertions(+)
 create mode 100644 arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts

diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
index 15d5e14fe418..9fff9e8be3de 100644
--- a/arch/loongarch/boot/dts/Makefile
+++ b/arch/loongarch/boot/dts/Makefile
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 dtb-y = loongson-2k0500-ref.dtb loongson-2k1000-ref.dtb loongson-2k2000-ref.dtb
+dtb-y += ls2k0300-ctcisz-forever-pi.dtb
diff --git a/arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts b/arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts
new file mode 100644
index 000000000000..a033c086461f
--- /dev/null
+++ b/arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
+ */
+
+/dts-v1/;
+
+#include "loongson-2k0300.dtsi"
+
+/ {
+	compatible = "ctcisz,forever-pi", "loongson,ls2k0300";
+	model = "CTCISZ Forever Pi";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	memory@200000 {
+		device_type = "memory";
+		reg = <0 0x00200000 0 0x0ee00000>,
+		      <0 0x90000000 0 0x10000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		linux,cma {
+			compatible = "shared-dma-pool";
+			reusable;
+			size = <0 0x02000000>;
+			linux,cma-default;
+		};
+	};
+};
+
+&uart0 {
+	clock-frequency = <100000000>;
+	status = "okay";
+};
-- 
2.49.0

Re: [PATCH v2 2/4] dt-bindings: LoongArch: Add CTCISZ Forever Pi

[Krzysztof Kozlowski]

On 18/05/2025 10:03, Yao Zi wrote:
> Forever Pi is an Loongson 2K0300-based development board produced by
> CTCISZ. Features include,
> 

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH v2 0/4] Initial support for CTCISZ Forever Pi

[Yanteng Si]

在 5/18/25 4:03 PM, Yao Zi 写道:
> This series adds support for CTCISZ Forever Pi, which ships an Loongson
> 2K0300 SoC and various peripherals. The vendor prefix and the board are
> documented and basic SoC/board devicetrees are added.
> 
> I've successfully booted into console with vendor U-Boot, a bootlog
> could be obtained here[1]. DTB and initramfs must be built into the
> kernel as the vendor bootloader cannot pass them and upstream U-Boot
> support for LoongArch is still WIP.
> 
> Thanks for your time and review.
> 
> [1]: https://gist.github.com/ziyao233/54ef900406876b5554f627d1ba0e130e
> 
> Changed from v1 ("Initial support for CTCISZ Ninenine Pi")
> - Board binding:
>    - Use "Forever Pi" instead of "Ninenine Pi" as translation of the
>      board model
> - SoC devicetree:
>    - Move UART aliases to the board dt
>    - Add the missing space in definition of liointc0
> - Link to v1: https://lore.kernel.org/all/20250501044239.9404-2-ziyao@disroot.org/
> 

> Yao Zi (4):
>    dt-bindings: vendor-prefixes: Add CTCISZ Technology Co., LTD.
>    dt-bindings: LoongArch: Add CTCISZ Forever Pi
>    LoongArch: dts: Add initial SoC devicetree for Loongson 2K0300
>    LoongArch: dts: Add initial devicetree for CTCISZ Forever Pi
> 
>   .../bindings/loongarch/loongson.yaml          |   5 +
>   .../devicetree/bindings/vendor-prefixes.yaml  |   2 +
>   arch/loongarch/boot/dts/Makefile              |   1 +
>   arch/loongarch/boot/dts/loongson-2k0300.dtsi  | 184 ++++++++++++++++++
>   .../boot/dts/ls2k0300-ctcisz-forever-pi.dts   |  45 +++++
>   5 files changed, 237 insertions(+)
For the patch sets.

Reviewed-by: Yanteng Si <si.yanteng@linux.dev>

Thanks,
Yanteng

Re: [PATCH v2 3/4] LoongArch: dts: Add initial SoC devicetree for Loongson 2K0300

[Binbin Zhou]

Hi Yao:

Thanks for your patch.

On Sun, May 18, 2025 at 4:05 PM Yao Zi <ziyao@disroot.org> wrote:
>
> Add SoC devicetree for 2K0300 SoC, which features one LA264 dual-issue
> core and targets embedded market. Only CPU core, legacy interrupt
> controllers and UARTs are defined for now.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/loongarch/boot/dts/loongson-2k0300.dtsi | 184 +++++++++++++++++++
>  1 file changed, 184 insertions(+)
>  create mode 100644 arch/loongarch/boot/dts/loongson-2k0300.dtsi
>
> diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
> new file mode 100644
> index 000000000000..17974f793947
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
> @@ -0,0 +1,184 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2025 Loongson Technology Corporation Limited
> + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/interrupt-controller/irq.h>
> +
> +/ {
> +       compatible = "loongson,ls2k0300";
> +       #address-cells = <2>;
> +       #size-cells = <2>;
> +
> +       cpus {
> +               #address-cells = <1>;
> +               #size-cells = <0>;
> +
> +               cpu0: cpu@0 {
> +                       compatible = "loongson,la264";
> +                       reg = <0>;
> +                       device_type = "cpu";
> +                       clocks = <&cpu_clk>;
> +               };
> +
> +       };
> +
> +       cpuintc: interrupt-controller {
> +               compatible = "loongson,cpu-interrupt-controller";
> +               interrupt-controller;
> +               #interrupt-cells = <1>;
> +       };
> +
> +       cpu_clk: clock-1000m {
> +               compatible = "fixed-clock";
> +               clock-frequency = <1000000000>;
> +               #clock-cells = <0>;
> +       };
> +
> +       soc {
I found the following warning while doing dtbs_check, please check again:

  DTC [C] arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dtb
arch/loongarch/boot/dts/loongson-2k0300.dtsi:41.6-183.4: Warning
(unit_address_vs_reg): /soc: node has a reg or ranges property, but no
unit name

> +               compatible = "simple-bus";
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges = <0x00 0x10000000 0x00 0x10000000 0x0 0x10000000>,
> +                        <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>,
> +                        <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>;
> +
> +               liointc0: interrupt-controller@16001400 {
> +                       compatible = "loongson,liointc-2.0";
> +                       reg = <0x0 0x16001400 0x0 0x40>,
> +                             <0x0 0x16001040 0x0 0x8>;
> +                       reg-names = "main", "isr0";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +
> +                       interrupt-parent = <&cpuintc>;
> +                       interrupts = <2>;
> +                       interrupt-names = "int0";
> +
> +                       loongson,parent_int_map = <0xffffffff>, /* int0 */
> +                                                 <0x00000000>, /* int1 */
> +                                                 <0x00000000>, /* int2 */
> +                                                 <0x00000000>; /* int3 */
> +               };
> +
> +               liointc1: interrupt-controller@16001440 {
> +                       compatible = "loongson,liointc-2.0";
> +                       reg = <0x0 0x16001440 0x0 0x40>,
> +                             <0x0 0x16001048 0x0 0x8>;
> +                       reg-names = "main", "isr0";
> +
> +                       interrupt-controller;
> +                       #interrupt-cells = <2>;
> +
> +                       interrupt-parent = <&cpuintc>;
> +                       interrupts = <4>;
> +                       interrupt-names = "int2";
> +
> +                       loongson,parent_int_map = <0x00000000>, /* int0 */
> +                                                 <0x00000000>, /* int1 */
> +                                                 <0xffffffff>, /* int2 */
> +                                                 <0x00000000>; /* int3 */
> +               };
> +
> +               uart0: serial@16100000 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16100000 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart1: serial@16100400 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16100400 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart2: serial@16100800 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16100800 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart3: serial@16100c00 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16100c00 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart4: serial@16101000 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16101000 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart5: serial@16101400 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16101400 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart6: serial@16101800 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16101800 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart7: serial@16101c00 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16101c00 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart8: serial@16102000 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16102000 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               uart9: serial@16102400 {
> +                       compatible = "ns16550a";
> +                       reg = <0 0x16102400 0 0x10>;
> +                       interrupt-parent = <&liointc0>;
> +                       interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
> +                       no-loopback-test;
> +                       status = "disabled";
> +               };
> +
> +               isa@16400000 {
> +                       compatible = "isa";
> +                       #address-cells = <2>;
> +                       #size-cells = <1>;
> +                       ranges = <1 0x0 0x0 0x16400000 0x4000>;
> +               };
> +       };
> +};
> --
> 2.49.0
>
>

-- 
Thanks.
Binbin

Re: [PATCH v2 3/4] LoongArch: dts: Add initial SoC devicetree for Loongson 2K0300

[Yao Zi]

On Mon, May 19, 2025 at 11:10:16AM +0800, Binbin Zhou wrote:
> Hi Yao:
> 
> Thanks for your patch.
> 
> On Sun, May 18, 2025 at 4:05 PM Yao Zi <ziyao@disroot.org> wrote:
> >
> > Add SoC devicetree for 2K0300 SoC, which features one LA264 dual-issue
> > core and targets embedded market. Only CPU core, legacy interrupt
> > controllers and UARTs are defined for now.
> >
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  arch/loongarch/boot/dts/loongson-2k0300.dtsi | 184 +++++++++++++++++++
> >  1 file changed, 184 insertions(+)
> >  create mode 100644 arch/loongarch/boot/dts/loongson-2k0300.dtsi
> >
> > diff --git a/arch/loongarch/boot/dts/loongson-2k0300.dtsi b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
> > new file mode 100644
> > index 000000000000..17974f793947
> > --- /dev/null
> > +++ b/arch/loongarch/boot/dts/loongson-2k0300.dtsi
> > @@ -0,0 +1,184 @@
> > +// SPDX-License-Identifier: GPL-2.0
> > +/*
> > + * Copyright (C) 2025 Loongson Technology Corporation Limited
> > + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/interrupt-controller/irq.h>
> > +
> > +/ {
> > +       compatible = "loongson,ls2k0300";
> > +       #address-cells = <2>;
> > +       #size-cells = <2>;
> > +
> > +       cpus {
> > +               #address-cells = <1>;
> > +               #size-cells = <0>;
> > +
> > +               cpu0: cpu@0 {
> > +                       compatible = "loongson,la264";
> > +                       reg = <0>;
> > +                       device_type = "cpu";
> > +                       clocks = <&cpu_clk>;
> > +               };
> > +
> > +       };
> > +
> > +       cpuintc: interrupt-controller {
> > +               compatible = "loongson,cpu-interrupt-controller";
> > +               interrupt-controller;
> > +               #interrupt-cells = <1>;
> > +       };
> > +
> > +       cpu_clk: clock-1000m {
> > +               compatible = "fixed-clock";
> > +               clock-frequency = <1000000000>;
> > +               #clock-cells = <0>;
> > +       };
> > +
> > +       soc {
> I found the following warning while doing dtbs_check, please check again:
> 
>   DTC [C] arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dtb
> arch/loongarch/boot/dts/loongson-2k0300.dtsi:41.6-183.4: Warning
> (unit_address_vs_reg): /soc: node has a reg or ranges property, but no
> unit name

Oops, seems -Wunit_address_vs_reg is silent without W=1 specified.
Commit 8654cb8d0371 (dtc: update warning settings for new bus and
node/property name checks, 2017-03-21) shows it's a temporary workaround
("Disable the new dtc warnings by default as there are 1000s").

I'll the node to soc@10000000 in v3. Thanks for catching something I've
never noticed before. Yanteng, is it okay for you to keep your
reviewed-by tag with the change?

> > +               compatible = "simple-bus";
> > +               #address-cells = <2>;
> > +               #size-cells = <2>;
> > +               ranges = <0x00 0x10000000 0x00 0x10000000 0x0 0x10000000>,
> > +                        <0x00 0x02000000 0x00 0x02000000 0x0 0x04000000>,
> > +                        <0x00 0x40000000 0x00 0x40000000 0x0 0x40000000>;
> > +

...

> > 2.49.0
> >
> >
> 
> -- 
> Thanks.
> Binbin
> 

Thanks,
Yao Zi

Re: [PATCH v2 4/4] LoongArch: dts: Add initial devicetree for CTCISZ Forever Pi

[Binbin Zhou]

Hi Yao:

On Sun, May 18, 2025 at 4:05 PM Yao Zi <ziyao@disroot.org> wrote:
>
> Enable UART0 as it's the boot UART used by firmware.
>
> Signed-off-by: Yao Zi <ziyao@disroot.org>
> ---
>  arch/loongarch/boot/dts/Makefile              |  1 +
>  .../boot/dts/ls2k0300-ctcisz-forever-pi.dts   | 45 +++++++++++++++++++

A minor suggestion:
As we can see, the existing dtsi/dts files are prefixed with
“loongosn-2k”, would it be possible to keep the filenames consistent?

>  2 files changed, 46 insertions(+)
>  create mode 100644 arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts
>
> diff --git a/arch/loongarch/boot/dts/Makefile b/arch/loongarch/boot/dts/Makefile
> index 15d5e14fe418..9fff9e8be3de 100644
> --- a/arch/loongarch/boot/dts/Makefile
> +++ b/arch/loongarch/boot/dts/Makefile
> @@ -1,3 +1,4 @@
>  # SPDX-License-Identifier: GPL-2.0-only
>
>  dtb-y = loongson-2k0500-ref.dtb loongson-2k1000-ref.dtb loongson-2k2000-ref.dtb
> +dtb-y += ls2k0300-ctcisz-forever-pi.dtb
> diff --git a/arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts b/arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts
> new file mode 100644
> index 000000000000..a033c086461f
> --- /dev/null
> +++ b/arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts
> @@ -0,0 +1,45 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2025 Yao Zi <ziyao@disroot.org>
> + */
> +
> +/dts-v1/;
> +
> +#include "loongson-2k0300.dtsi"
> +
> +/ {
> +       compatible = "ctcisz,forever-pi", "loongson,ls2k0300";
> +       model = "CTCISZ Forever Pi";
> +
> +       aliases {
> +               serial0 = &uart0;
> +       };
> +
> +       chosen {
> +               stdout-path = "serial0:115200n8";
> +       };
> +
> +       memory@200000 {
> +               device_type = "memory";
> +               reg = <0 0x00200000 0 0x0ee00000>,
> +                     <0 0x90000000 0 0x10000000>;
> +       };
> +
> +       reserved-memory {
> +               #address-cells = <2>;
> +               #size-cells = <2>;
> +               ranges;
> +
> +               linux,cma {
> +                       compatible = "shared-dma-pool";
> +                       reusable;
> +                       size = <0 0x02000000>;
> +                       linux,cma-default;
> +               };
> +       };
> +};
> +
> +&uart0 {
> +       clock-frequency = <100000000>;
> +       status = "okay";
> +};
> --
> 2.49.0
>
>

-- 
Thanks.
Binbin

Re: [PATCH v2 4/4] LoongArch: dts: Add initial devicetree for CTCISZ Forever Pi

[Yao Zi]

On Mon, May 19, 2025 at 03:58:29PM +0800, Binbin Zhou wrote:
> Hi Yao:
> 
> On Sun, May 18, 2025 at 4:05 PM Yao Zi <ziyao@disroot.org> wrote:
> >
> > Enable UART0 as it's the boot UART used by firmware.
> >
> > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > ---
> >  arch/loongarch/boot/dts/Makefile              |  1 +
> >  .../boot/dts/ls2k0300-ctcisz-forever-pi.dts   | 45 +++++++++++++++++++
> 
> A minor suggestion:
> As we can see, the existing dtsi/dts files are prefixed with
> “loongosn-2k”, would it be possible to keep the filenames consistent?

It's abbreviated since loongson-2k0300-ctcisz-forever-pi.dts seems a
little too long for me, and naming devicetree files in form of
<abbreviated-SoC-name>-<vendor>-<model> is common on other
architectures.

I won't insist and will change it if you consider consistency really
matters.

> >  2 files changed, 46 insertions(+)
> >  create mode 100644 arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts

...

> -- 
> Thanks.
> Binbin

Best regards,
Yao Zi

Re: [PATCH v2 4/4] LoongArch: dts: Add initial devicetree for CTCISZ Forever Pi

[Binbin Zhou]

On Mon, May 19, 2025 at 5:43 PM Yao Zi <ziyao@disroot.org> wrote:
>
> On Mon, May 19, 2025 at 03:58:29PM +0800, Binbin Zhou wrote:
> > Hi Yao:
> >
> > On Sun, May 18, 2025 at 4:05 PM Yao Zi <ziyao@disroot.org> wrote:
> > >
> > > Enable UART0 as it's the boot UART used by firmware.
> > >
> > > Signed-off-by: Yao Zi <ziyao@disroot.org>
> > > ---
> > >  arch/loongarch/boot/dts/Makefile              |  1 +
> > >  .../boot/dts/ls2k0300-ctcisz-forever-pi.dts   | 45 +++++++++++++++++++
> >
> > A minor suggestion:
> > As we can see, the existing dtsi/dts files are prefixed with
> > “loongosn-2k”, would it be possible to keep the filenames consistent?
>
> It's abbreviated since loongson-2k0300-ctcisz-forever-pi.dts seems a
> little too long for me, and naming devicetree files in form of
> <abbreviated-SoC-name>-<vendor>-<model> is common on other
> architectures.

Sorry, the length of the filename is not really a major concern for me.
>
> I won't insist and will change it if you consider consistency really
> matters.

Yes, I actually do mind, let's keep the naming consistent.
>
> > >  2 files changed, 46 insertions(+)
> > >  create mode 100644 arch/loongarch/boot/dts/ls2k0300-ctcisz-forever-pi.dts
>
> ...
>
> > --
> > Thanks.
> > Binbin
>
> Best regards,
> Yao Zi

-- 
Thanks.
Binbin