From: Petr Vorel <pvorel@suse.cz>
To: Hui Min Mina Chou <minachou@andestech.com>
Cc: tim609@andestech.com, cynthia@andestech.com, az70021@gmail.com,
ltp@lists.linux.it
Subject: Re: [LTP] [PATCH] hugemmap15: Support RISC-V to do __cache_flush. (#79)
Date: Thu, 9 May 2024 10:06:49 +0200 [thread overview]
Message-ID: <20240509080649.GB234264@pevik> (raw)
In-Reply-To: <20240509052541.18707-1-minachou@andestech.com>
Hi Hui,
> AndesCore CPU test fails due to an illegal instruction at the first
> jumpfunc(), caused by executing incorrect instructions after
> self-modifying code.
> On RISC-V CPUs, a FENCE.i synchronizes instruction and data streams,
> ensuring that subsequent instruction fetch on a RISC-V hart will see
> any previous data stores already visible to the same RISC-V hart.
> Thus, cacheflush() in the test should also use __clear_cache for RISC-V.
> In SMP systems, it invokes the kernel syscall riscv_flush_icache to inform
> each hart to flush their local i-caches.
Reviewed-by: Petr Vorel <pvorel@suse.cz>
BTW what "#79" in the git message subject means?
Kind regards,
Petr
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Mailing list info: https://lists.linux.it/listinfo/ltp
next prev parent reply other threads:[~2024-05-09 8:07 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-05-09 5:25 [LTP] [PATCH] hugemmap15: Support RISC-V to do __cache_flush. (#79) Hui Min Mina Chou via ltp
2024-05-09 8:06 ` Petr Vorel [this message]
2024-05-09 8:34 ` [LTP] [PATCH] hugemmap15: Support RISC-V to do __cache_flush Mina Chou via ltp
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