[LTP] [PATCH] high_freq_hwp_cap_cppc.c: new test

[LTP] [PATCH] high_freq_hwp_cap_cppc.c: new test

[Piotr Kubaj]

Verify for all online logical CPUs that their highest performance value are
the same for HWP Capability MSR 0x771 and CPPC sysfs file.
---
 testcases/kernel/power_management/.gitignore  |  1 +
 .../power_management/high_freq_hwp_cap_cppc.c | 57 +++++++++++++++++++
 2 files changed, 58 insertions(+)
 create mode 100644 testcases/kernel/power_management/high_freq_hwp_cap_cppc.c

diff --git a/testcases/kernel/power_management/.gitignore b/testcases/kernel/power_management/.gitignore
index 0c2a3ed4b..c13bca1c4 100644
--- a/testcases/kernel/power_management/.gitignore
+++ b/testcases/kernel/power_management/.gitignore
@@ -1 +1,2 @@
+high_freq_hwp_cap_cppc
 pm_get_sched_values
diff --git a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
new file mode 100644
index 000000000..4cbb81f0b
--- /dev/null
+++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
@@ -0,0 +1,57 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Copyright (C) 2025-2026 Intel - http://www.intel.com/
+ */
+
+/*\
+ * Verify for all online logical CPUs  that their highest performance value are
+ * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
+ */
+
+#include "tst_test.h"
+
+static int nproc;
+
+static void setup(void)
+{
+	nproc = tst_ncpus();
+}
+
+static void run(void)
+{
+	for (int i = 0; i < nproc; i++) {
+		char path[PATH_MAX];
+		unsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;
+
+		snprintf(path, PATH_MAX, "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
+		SAFE_FILE_SCANF(path, "%llu", &sysfs_highest_perf);
+		tst_res(TDEBUG, "%s: %llu", path, sysfs_highest_perf);
+
+		snprintf(path, PATH_MAX, "/dev/cpu/%d/msr", i);
+		int fd = SAFE_OPEN(path, O_RDONLY);
+
+		if (pread(fd, &msr_highest_perf, sizeof(msr_highest_perf), 0x771) < 0) {
+			SAFE_CLOSE(fd);
+			tst_brk(TBROK | TERRNO, "MSR read error");
+		}
+		SAFE_CLOSE(fd);
+		msr_highest_perf &= (1ULL << 8) - 1;
+		tst_res(TDEBUG, "%s: %llu", path, msr_highest_perf);
+
+		if (msr_highest_perf != sysfs_highest_perf)
+			tst_brk(TFAIL, "CPU %d: highest performance values differ between sysfs and MSR", i);
+	}
+
+	tst_res(TPASS, "Test pass");
+}
+
+static struct tst_test test = {
+	.needs_kconfigs = (const char *const []) {
+		"CONFIG_X86_MSR",
+		NULL
+	},
+	.needs_root = 1,
+	.setup = setup,
+	.test_all = run
+};
-- 
2.47.3

---------------------------------------------------------------------
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Re: [LTP] [PATCH] high_freq_hwp_cap_cppc.c: new test

[Petr Vorel]

Hi Piotr,

> Verify for all online logical CPUs that their highest performance value are
> the same for HWP Capability MSR 0x771 and CPPC sysfs file.

You were supposed to add your RBT:
Signed-off-by: Piotr Kubaj <piotr.kubaj@intel.com>

> ---
>  testcases/kernel/power_management/.gitignore  |  1 +
>  .../power_management/high_freq_hwp_cap_cppc.c | 57 +++++++++++++++++++

You did not add test into runtest/thermal. OTOH test will apply also after we
finally merge thermal_interrupt_events.c.

>  2 files changed, 58 insertions(+)
>  create mode 100644 testcases/kernel/power_management/high_freq_hwp_cap_cppc.c

> diff --git a/testcases/kernel/power_management/.gitignore b/testcases/kernel/power_management/.gitignore
> index 0c2a3ed4b..c13bca1c4 100644
> --- a/testcases/kernel/power_management/.gitignore
> +++ b/testcases/kernel/power_management/.gitignore
> @@ -1 +1,2 @@
> +high_freq_hwp_cap_cppc
>  pm_get_sched_values
> diff --git a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> new file mode 100644
> index 000000000..4cbb81f0b
> --- /dev/null
> +++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +/*
> + * Copyright (C) 2025-2026 Intel - http://www.intel.com/
> + */
> +
> +/*\
> + * Verify for all online logical CPUs  that their highest performance value are
> + * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> + */
> +
> +#include "tst_test.h"
> +
> +static int nproc;
> +
> +static void setup(void)
> +{
> +	nproc = tst_ncpus();
> +}
> +
> +static void run(void)
> +{
> +	for (int i = 0; i < nproc; i++) {
> +		char path[PATH_MAX];
> +		unsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;
> +
> +		snprintf(path, PATH_MAX, "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
> +		SAFE_FILE_SCANF(path, "%llu", &sysfs_highest_perf);

I tried to run the test, but it fails due missing sysfs file:

$ grep CONFIG_X86_MSR /boot/config-6.19.0-rc1-1.g274aff5-default 
CONFIG_X86_MSR=m

$ lsmod |grep msr
intel_rapl_msr         20480  0
intel_rapl_common      53248  1 intel_rapl_msr

# ./high_freq_hwp_cap_cppc 
tst_test.c:1887: TINFO: Overall timeout per run is 0h 02m 00s
...
high_freq_hwp_cap_cppc.c:28: TBROK: Failed to open FILE '/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf' for reading: ENOENT (2)

# modprobe msr

$ lsmod |grep msr
msr                    12288  0
intel_rapl_msr         20480  0
intel_rapl_common      53248  1 intel_rapl_msr

# ./high_freq_hwp_cap_cppc
...
high_freq_hwp_cap_cppc.c:28: TBROK: Failed to open FILE '/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf' for reading: ENOENT (2)

=> obviously checking for CONFIG_X86_MSR is not enough.

OT: it'd be nice to extend 'save_restore' library functionality to
1) support glob (/sys/devices/system/cpu/cpu*/acpi_cppc/highest_perf)
2) read value into the variable (in case of glob into array).

> +		tst_res(TDEBUG, "%s: %llu", path, sysfs_highest_perf);
> +
> +		snprintf(path, PATH_MAX, "/dev/cpu/%d/msr", i);
> +		int fd = SAFE_OPEN(path, O_RDONLY);
> +
> +		if (pread(fd, &msr_highest_perf, sizeof(msr_highest_perf), 0x771) < 0) {
> +			SAFE_CLOSE(fd);
> +			tst_brk(TBROK | TERRNO, "MSR read error");
> +		}
> +		SAFE_CLOSE(fd);
> +		msr_highest_perf &= (1ULL << 8) - 1;
> +		tst_res(TDEBUG, "%s: %llu", path, msr_highest_perf);
> +
> +		if (msr_highest_perf != sysfs_highest_perf)
> +			tst_brk(TFAIL, "CPU %d: highest performance values differ between sysfs and MSR", i);
> +	}
> +
> +	tst_res(TPASS, "Test pass");

"Test pass" has zero information value.
Maybe something like:
"sysfs and MSR values are equal"

> +}
> +
> +static struct tst_test test = {
> +	.needs_kconfigs = (const char *const []) {
> +		"CONFIG_X86_MSR",
> +		NULL
> +	},
For thermal_interrupt_events.c we also have use .supported_archs (for the docs
purposes), why not to add it to this test as well?

+	.supported_archs = (const char *const []) {
+		"x86",
+		"x86_64",
+		NULL
+	},

Kind regards,
Petr

> +	.needs_root = 1,
> +	.setup = setup,
> +	.test_all = run
> +};

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Re: [LTP] [PATCH] high_freq_hwp_cap_cppc.c: new test

[Andrea Cervesato via ltp]

Hi!

> Verify for all online logical CPUs that their highest performance value are
> the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> ---
>  testcases/kernel/power_management/.gitignore  |  1 +
>  .../power_management/high_freq_hwp_cap_cppc.c | 57 +++++++++++++++++++
>  2 files changed, 58 insertions(+)
>  create mode 100644 testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> 
> diff --git a/testcases/kernel/power_management/.gitignore b/testcases/kernel/power_management/.gitignore
> index 0c2a3ed4b..c13bca1c4 100644
> --- a/testcases/kernel/power_management/.gitignore
> +++ b/testcases/kernel/power_management/.gitignore
> @@ -1 +1,2 @@
> +high_freq_hwp_cap_cppc
>  pm_get_sched_values
> diff --git a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> new file mode 100644
> index 000000000..4cbb81f0b
> --- /dev/null
> +++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> @@ -0,0 +1,57 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +
> +/*
> + * Copyright (C) 2025-2026 Intel - http://www.intel.com/
> + */

Remove space
> +
> +/*\
> + * Verify for all online logical CPUs  that their highest performance value are

Double space before "that"

> + * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> + */
> +
> +#include "tst_test.h"
> +
> +static int nproc;
> +
> +static void setup(void)
> +{
> +	nproc = tst_ncpus();
> +}
> +
> +static void run(void)
> +{
> +	for (int i = 0; i < nproc; i++) {
> +		char path[PATH_MAX];
> +		unsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;
> +
> +		snprintf(path, PATH_MAX, "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);

snprintf(path, sizeof(path), ..) is better.

> +		SAFE_FILE_SCANF(path, "%llu", &sysfs_highest_perf);
> +		tst_res(TDEBUG, "%s: %llu", path, sysfs_highest_perf);
> +
> +		snprintf(path, PATH_MAX, "/dev/cpu/%d/msr", i);
> +		int fd = SAFE_OPEN(path, O_RDONLY);
> +
> +		if (pread(fd, &msr_highest_perf, sizeof(msr_highest_perf), 0x771) < 0) {
> +			SAFE_CLOSE(fd);
> +			tst_brk(TBROK | TERRNO, "MSR read error");
> +		}

Simply use SAFE_PREAD(). fd will be closed when test ends.

> +		SAFE_CLOSE(fd);
> +		msr_highest_perf &= (1ULL << 8) - 1;
> +		tst_res(TDEBUG, "%s: %llu", path, msr_highest_perf);
> +
> +		if (msr_highest_perf != sysfs_highest_perf)
> +			tst_brk(TFAIL, "CPU %d: highest performance values differ between sysfs and MSR", i);

Why tst_brk() ? It's supposed to be tst_res(TFAIL, ..).

> +	}
> +
> +	tst_res(TPASS, "Test pass");
> +}
> +
> +static struct tst_test test = {
> +	.needs_kconfigs = (const char *const []) {
> +		"CONFIG_X86_MSR",

The CPPC sysfs interface also requires CONFIG_ACPI_CPPC_LIB to be built.

> +		NULL
> +	},
> +	.needs_root = 1,
> +	.setup = setup,
> +	.test_all = run
> +};
> -- 
> 2.47.3
> 
> ---------------------------------------------------------------------
> Intel Technology Poland sp. z o.o.
> ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
> Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.
> 
> Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
> This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.
> 
> 
> -- 
> Mailing list info: https://lists.linux.it/listinfo/ltp

There's also no runtest entry for this test, so it can't be run in the testing
suites by kirk.

Kind regards,
--
Andrea Cervesato
SUSE QE Automation Engineer Linux
andrea.cervesato@suse.com

-- 
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Re: [LTP] [PATCH] high_freq_hwp_cap_cppc.c: new test

[Kubaj, Piotr]

2026-03-16 (月) の 13:33 +0100 に Petr Vorel さんは書きました:
> Hi Piotr,
> 
> > Verify for all online logical CPUs that their highest performance
> > value are
> > the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> 
> You were supposed to add your RBT:
> Signed-off-by: Piotr Kubaj <piotr.kubaj@intel.com>
> 
> > ---
> >  testcases/kernel/power_management/.gitignore  |  1 +
> >  .../power_management/high_freq_hwp_cap_cppc.c | 57
> > +++++++++++++++++++
> 
> You did not add test into runtest/thermal. OTOH test will apply also
> after we
> finally merge thermal_interrupt_events.c.

It's actually not thermal-related, but there are going to be more
thermal tests anyway.

> 
> >  2 files changed, 58 insertions(+)
> >  create mode 100644
> > testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> 
> > diff --git a/testcases/kernel/power_management/.gitignore
> > b/testcases/kernel/power_management/.gitignore
> > index 0c2a3ed4b..c13bca1c4 100644
> > --- a/testcases/kernel/power_management/.gitignore
> > +++ b/testcases/kernel/power_management/.gitignore
> > @@ -1 +1,2 @@
> > +high_freq_hwp_cap_cppc
> >  pm_get_sched_values
> > diff --git
> > a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > new file mode 100644
> > index 000000000..4cbb81f0b
> > --- /dev/null
> > +++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > @@ -0,0 +1,57 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +
> > +/*
> > + * Copyright (C) 2025-2026 Intel - http://www.intel.com/
> > + */
> > +
> > +/*\
> > + * Verify for all online logical CPUs  that their highest
> > performance value are
> > + * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> > + */
> > +
> > +#include "tst_test.h"
> > +
> > +static int nproc;
> > +
> > +static void setup(void)
> > +{
> > +	nproc = tst_ncpus();
> > +}
> > +
> > +static void run(void)
> > +{
> > +	for (int i = 0; i < nproc; i++) {
> > +		char path[PATH_MAX];
> > +		unsigned long long msr_highest_perf = 0,
> > sysfs_highest_perf = 0;
> > +
> > +		snprintf(path, PATH_MAX,
> > "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
> > +		SAFE_FILE_SCANF(path, "%llu",
> > &sysfs_highest_perf);
> 
> I tried to run the test, but it fails due missing sysfs file:
> 
> $ grep CONFIG_X86_MSR /boot/config-6.19.0-rc1-1.g274aff5-default 
> CONFIG_X86_MSR=m
> 
> $ lsmod |grep msr
> intel_rapl_msr         20480  0
> intel_rapl_common      53248  1 intel_rapl_msr
> 
> # ./high_freq_hwp_cap_cppc 
> tst_test.c:1887: TINFO: Overall timeout per run is 0h 02m 00s
> ...
> high_freq_hwp_cap_cppc.c:28: TBROK: Failed to open FILE
> '/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf' for reading:
> ENOENT (2)
> 
> # modprobe msr
> 
> $ lsmod |grep msr
> msr                    12288  0
> intel_rapl_msr         20480  0
> intel_rapl_common      53248  1 intel_rapl_msr
> 
> # ./high_freq_hwp_cap_cppc
> ...
> high_freq_hwp_cap_cppc.c:28: TBROK: Failed to open FILE
> '/sys/devices/system/cpu/cpu0/acpi_cppc/highest_perf' for reading:
> ENOENT (2)
> 
> => obviously checking for CONFIG_X86_MSR is not enough.
Right, CONFIG_ACPI_CPPC_LIB is also necessary.

> 
> OT: it'd be nice to extend 'save_restore' library functionality to
> 1) support glob (/sys/devices/system/cpu/cpu*/acpi_cppc/highest_perf)
> 2) read value into the variable (in case of glob into array).
> 
> > +		tst_res(TDEBUG, "%s: %llu", path,
> > sysfs_highest_perf);
> > +
> > +		snprintf(path, PATH_MAX, "/dev/cpu/%d/msr", i);
> > +		int fd = SAFE_OPEN(path, O_RDONLY);
> > +
> > +		if (pread(fd, &msr_highest_perf,
> > sizeof(msr_highest_perf), 0x771) < 0) {
> > +			SAFE_CLOSE(fd);
> > +			tst_brk(TBROK | TERRNO, "MSR read error");
> > +		}
> > +		SAFE_CLOSE(fd);
> > +		msr_highest_perf &= (1ULL << 8) - 1;
> > +		tst_res(TDEBUG, "%s: %llu", path,
> > msr_highest_perf);
> > +
> > +		if (msr_highest_perf != sysfs_highest_perf)
> > +			tst_brk(TFAIL, "CPU %d: highest
> > performance values differ between sysfs and MSR", i);
> > +	}
> > +
> > +	tst_res(TPASS, "Test pass");
> 
> "Test pass" has zero information value.
> Maybe something like:
> "sysfs and MSR values are equal"
Done.

> 
> > +}
> > +
> > +static struct tst_test test = {
> > +	.needs_kconfigs = (const char *const []) {
> > +		"CONFIG_X86_MSR",
> > +		NULL
> > +	},
> For thermal_interrupt_events.c we also have use .supported_archs (for
> the docs
> purposes), why not to add it to this test as well?
I removed it for the same reason that was mentioned in the review for
thermal_interrupt_events.c. MSR is x86- and x86_64-only. Added in the
newer version.
> 
> +	.supported_archs = (const char *const []) {
> +		"x86",
> +		"x86_64",
> +		NULL
> +	},
> 
> Kind regards,
> Petr
> 
> > +	.needs_root = 1,
> > +	.setup = setup,
> > +	.test_all = run
> > +};
---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.

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Re: [LTP] [PATCH] high_freq_hwp_cap_cppc.c: new test

[Kubaj, Piotr]

2026-03-16 (月) の 12:55 +0000 に Andrea Cervesato さんは書きました:
> Hi!
> 
> > Verify for all online logical CPUs that their highest performance
> > value are
> > the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> > ---
> >  testcases/kernel/power_management/.gitignore  |  1 +
> >  .../power_management/high_freq_hwp_cap_cppc.c | 57
> > +++++++++++++++++++
> >  2 files changed, 58 insertions(+)
> >  create mode 100644
> > testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > 
> > diff --git a/testcases/kernel/power_management/.gitignore
> > b/testcases/kernel/power_management/.gitignore
> > index 0c2a3ed4b..c13bca1c4 100644
> > --- a/testcases/kernel/power_management/.gitignore
> > +++ b/testcases/kernel/power_management/.gitignore
> > @@ -1 +1,2 @@
> > +high_freq_hwp_cap_cppc
> >  pm_get_sched_values
> > diff --git
> > a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > new file mode 100644
> > index 000000000..4cbb81f0b
> > --- /dev/null
> > +++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
> > @@ -0,0 +1,57 @@
> > +// SPDX-License-Identifier: GPL-2.0-or-later
> > +
> > +/*
> > + * Copyright (C) 2025-2026 Intel - http://www.intel.com/
> > + */
> 
> Remove space
Do you mean that double space? Removed. Other than that, I couldn't
find any redundant space.

> > +
> > +/*\
> > + * Verify for all online logical CPUs  that their highest
> > performance value are
> 
> Double space before "that"
> 
> > + * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
> > + */
> > +
> > +#include "tst_test.h"
> > +
> > +static int nproc;
> > +
> > +static void setup(void)
> > +{
> > +	nproc = tst_ncpus();
> > +}
> > +
> > +static void run(void)
> > +{
> > +	for (int i = 0; i < nproc; i++) {
> > +		char path[PATH_MAX];
> > +		unsigned long long msr_highest_perf = 0,
> > sysfs_highest_perf = 0;
> > +
> > +		snprintf(path, PATH_MAX,
> > "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
> 
> snprintf(path, sizeof(path), ..) is better.
Done.

> 
> > +		SAFE_FILE_SCANF(path, "%llu",
> > &sysfs_highest_perf);
> > +		tst_res(TDEBUG, "%s: %llu", path,
> > sysfs_highest_perf);
> > +
> > +		snprintf(path, PATH_MAX, "/dev/cpu/%d/msr", i);
> > +		int fd = SAFE_OPEN(path, O_RDONLY);
> > +
> > +		if (pread(fd, &msr_highest_perf,
> > sizeof(msr_highest_perf), 0x771) < 0) {
> > +			SAFE_CLOSE(fd);
> > +			tst_brk(TBROK | TERRNO, "MSR read error");
> > +		}
> 
> Simply use SAFE_PREAD(). fd will be closed when test ends.
Done.

> 
> > +		SAFE_CLOSE(fd);
> > +		msr_highest_perf &= (1ULL << 8) - 1;
> > +		tst_res(TDEBUG, "%s: %llu", path,
> > msr_highest_perf);
> > +
> > +		if (msr_highest_perf != sysfs_highest_perf)
> > +			tst_brk(TFAIL, "CPU %d: highest
> > performance values differ between sysfs and MSR", i);
> 
> Why tst_brk() ? It's supposed to be tst_res(TFAIL, ..).
I actually find tst_brk() cleaner, because it ends the test when
there's a failure which removes the need for a check later, but I
changed it according to your suggestion.

> 
> > +	}
> > +
> > +	tst_res(TPASS, "Test pass");
> > +}
> > +
> > +static struct tst_test test = {
> > +	.needs_kconfigs = (const char *const []) {
> > +		"CONFIG_X86_MSR",
> 
> The CPPC sysfs interface also requires CONFIG_ACPI_CPPC_LIB to be
> built.
Right, added.

> 
> > +		NULL
> > +	},
> > +	.needs_root = 1,
> > +	.setup = setup,
> > +	.test_all = run
> > +};
> > -- 
> > 2.47.3
> > 
> > -------------------------------------------------------------------
> > --
> > Intel Technology Poland sp. z o.o.
> > ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc |
> > VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 |
> > NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
> > Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w
> > rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu
> > nadmiernym opoznieniom w transakcjach handlowych.
> > 
> > Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego
> > adresata i moze zawierac informacje poufne. W razie przypadkowego
> > otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz
> > trwale jej usuniecie; jakiekolwiek przegladanie lub
> > rozpowszechnianie jest zabronione.
> > This e-mail and any attachments may contain confidential material
> > for the sole use of the intended recipient(s). If you are not the
> > intended recipient, please contact the sender and delete all
> > copies; any review or distribution by others is strictly
> > prohibited.
> > 
> > 
> > -- 
> > Mailing list info: https://lists.linux.it/listinfo/ltp
> 
> There's also no runtest entry for this test, so it can't be run in
> the testing
> suites by kirk.
> 
> Kind regards,
> --
> Andrea Cervesato
> SUSE QE Automation Engineer Linux
> andrea.cervesato@suse.com
---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
This e-mail and any attachments may contain confidential material for the sole use of the intended recipient(s). If you are not the intended recipient, please contact the sender and delete all copies; any review or distribution by others is strictly prohibited.

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Re: [LTP] [PATCH] high_freq_hwp_cap_cppc.c: new test

[Petr Vorel]

> > Hi Piotr,

> > > Verify for all online logical CPUs that their highest performance
> > > value are
> > > the same for HWP Capability MSR 0x771 and CPPC sysfs file.

> > You were supposed to add your RBT:
> > Signed-off-by: Piotr Kubaj <piotr.kubaj@intel.com>

> > > ---
> > >  testcases/kernel/power_management/.gitignore  |  1 +
> > >  .../power_management/high_freq_hwp_cap_cppc.c | 57
> > > +++++++++++++++++++

> > You did not add test into runtest/thermal. OTOH test will apply also
> > after we
> > finally merge thermal_interrupt_events.c.

> It's actually not thermal-related, but there are going to be more
> thermal tests anyway.

I'm sorry, I overlooked power_management directory. Anyway, even in new v2
you haven't added a new test into any runtest file.

Kind regards,
Petr

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