[LTP] [PATCH v6] high_freq_hwp_cap_cppc.c: new test

[LTP] [PATCH v6] high_freq_hwp_cap_cppc.c: new test

[Piotr Kubaj]

Verify for all online logical CPUs that their highest performance value are
the same for HWP Capability MSR 0x771 and CPPC sysfs file.

Signed-off-by: Piotr Kubaj <piotr.kubaj@intel.com>
---
Online check needs to be true by default for cpu0 to be checked.

 runtest/power_management_tests                |  1 +
 testcases/kernel/power_management/.gitignore  |  1 +
 .../power_management/high_freq_hwp_cap_cppc.c | 84 +++++++++++++++++++
 3 files changed, 86 insertions(+)
 create mode 100644 testcases/kernel/power_management/high_freq_hwp_cap_cppc.c

diff --git a/runtest/power_management_tests b/runtest/power_management_tests
index 884e615cd..6d87dfb7f 100644
--- a/runtest/power_management_tests
+++ b/runtest/power_management_tests
@@ -1,4 +1,5 @@
 #POWER_MANAGEMENT
+high_freq_hwp_cap_cppc high_freq_hwp_cap_cppc
 runpwtests01 runpwtests01.sh
 runpwtests02 runpwtests02.sh
 runpwtests03 runpwtests03.sh
diff --git a/testcases/kernel/power_management/.gitignore b/testcases/kernel/power_management/.gitignore
index 0c2a3ed4b..c13bca1c4 100644
--- a/testcases/kernel/power_management/.gitignore
+++ b/testcases/kernel/power_management/.gitignore
@@ -1 +1,2 @@
+high_freq_hwp_cap_cppc
 pm_get_sched_values
diff --git a/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
new file mode 100644
index 000000000..7f604d253
--- /dev/null
+++ b/testcases/kernel/power_management/high_freq_hwp_cap_cppc.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * Copyright (C) 2026 Intel - http://www.intel.com/
+ */
+
+/*\
+ * Verify for all online logical CPUs that their highest performance value are
+ * the same for HWP Capability MSR 0x771 and CPPC sysfs file.
+ */
+
+#include "tst_test.h"
+#include "tst_safe_prw.h"
+
+static int nproc;
+
+static void setup(void)
+{
+	nproc = tst_ncpus();
+}
+
+static void run(void)
+{
+	bool status = true;
+
+	for (int i = 0; i < nproc; i++) {
+		bool online = true;
+		char path[PATH_MAX];
+		unsigned long long msr_highest_perf = 0, sysfs_highest_perf = 0;
+
+		snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/online", i);
+		if (i)
+			SAFE_FILE_SCANF(path, "%d", &online);
+
+		if (!online) {
+			tst_res(TINFO, "CPU%d offline, skipping", i);
+			continue;
+		}
+
+		snprintf(path, sizeof(path), "/sys/devices/system/cpu/cpu%d/acpi_cppc/highest_perf", i);
+		if (access(path, F_OK) == -1) {
+			tst_res(TCONF | TERRNO, "CPPC sysfs not available, skipping");
+			return;
+		}
+
+		SAFE_FILE_SCANF(path, "%llu", &sysfs_highest_perf);
+		tst_res(TDEBUG, "%s: %llu", path, sysfs_highest_perf);
+
+		snprintf(path, sizeof(path), "/dev/cpu/%d/msr", i);
+		int fd = SAFE_OPEN(path, O_RDONLY);
+
+		SAFE_PREAD(1, fd, &msr_highest_perf, sizeof(msr_highest_perf), 0x771);
+		msr_highest_perf &= (1ULL << 8) - 1;
+		tst_res(TDEBUG, "%s: %llu", path, msr_highest_perf);
+
+		if (msr_highest_perf != sysfs_highest_perf) {
+			tst_res(TINFO, "cpu%d: sysfs=%llu MSR=%llu",
+				i, sysfs_highest_perf, msr_highest_perf);
+			status = false;
+		}
+
+		SAFE_CLOSE(fd);
+	}
+
+	if (status)
+		tst_res(TPASS, "Sysfs and MSR values are equal");
+	else
+		tst_res(TFAIL, "Highest performance values differ between sysfs and MSR");
+}
+
+static struct tst_test test = {
+	.needs_kconfigs = (const char *const []) {
+		"CONFIG_ACPI_CPPC_LIB",
+		"CONFIG_X86_MSR",
+		NULL
+	},
+	.needs_root = 1,
+	.setup = setup,
+	.supported_archs = (const char *const []) {
+		"x86",
+		"x86_64",
+		NULL
+	},
+	.test_all = run
+};
-- 
2.47.3

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Re: [LTP] [PATCH v6] high_freq_hwp_cap_cppc.c: new test

[Andrea Cervesato via ltp]

Hi Piotr,

Thanks for the new test. A few issues below.

> +/*
> + * Copyright (C) 2026 Intel - http://www.intel.com/
> + */

The copyright line should include an author name and email, e.g.:

  Copyright (c) 2026 Piotr Kubaj <piotr.kubaj@intel.com>

> +		if (i)
> +			SAFE_FILE_SCANF(path, "%d", &online);

SAFE_FILE_SCANF with "%d" expects a pointer to int, but `online` is
bool (typically 1 byte). This is undefined behavior and will likely
corrupt the stack on little-endian. Please use `int online = 1;`
instead.

This should be spotted by any static analyzer or clangd..and even
gcc shows this error.

> +		snprintf(path, sizeof(path), "/dev/cpu/%d/msr", i);
> +		int fd = SAFE_OPEN(path, O_RDONLY);
> +
> +		SAFE_PREAD(1, fd, &msr_highest_perf, sizeof(msr_highest_perf), 0x771);

SAFE_CLOSE(fd) right after it has been used. There's no need to keep it
open after pread().

> +		msr_highest_perf &= (1ULL << 8) - 1;

0x771 and the 8-bit mask are magic numbers. Named defines would
help readability, e.g.:

  #define MSR_HWP_CAPABILITIES  0x771
  #define HIGHEST_PERF_MASK     0xFF

The test fails because msr device is not available, so you need:

  .needs_drivers = (const char *const []) {                                                                                                        
      "msr",                                                                                                                                       
      NULL                                                                                                                                         
  },

And probably the CONFIG_X86_MSR=y check as well.

Regards,
--
Andrea Cervesato
SUSE QE Automation Engineer Linux
andrea.cervesato@suse.com

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Re: [LTP] [PATCH v6] high_freq_hwp_cap_cppc.c: new test

[Kubaj, Piotr]

2026-03-25 (水) の 12:24 +0000 に Andrea Cervesato さんは書きました:
> Hi Piotr,
> 
> Thanks for the new test. A few issues below.
> 
> > +/*
> > + * Copyright (C) 2026 Intel - http://www.intel.com/
> > + */
> 
> The copyright line should include an author name and email, e.g.:
> 
>   Copyright (c) 2026 Piotr Kubaj <piotr.kubaj@intel.com>
> 
> > +		if (i)
> > +			SAFE_FILE_SCANF(path, "%d", &online);
> 
> SAFE_FILE_SCANF with "%d" expects a pointer to int, but `online` is
> bool (typically 1 byte). This is undefined behavior and will likely
> corrupt the stack on little-endian. Please use `int online = 1;`
> instead.
> 
> This should be spotted by any static analyzer or clangd..and even
> gcc shows this error.
For the record: 
GCC does NOT print a warning while compiling that code. At least with
the default set of options when building on Debian 13 with stock GCC
14.2.0.

> 
> > +		snprintf(path, sizeof(path), "/dev/cpu/%d/msr",
> > i);
> > +		int fd = SAFE_OPEN(path, O_RDONLY);
> > +
> > +		SAFE_PREAD(1, fd, &msr_highest_perf,
> > sizeof(msr_highest_perf), 0x771);
> 
> SAFE_CLOSE(fd) right after it has been used. There's no need to keep
> it
> open after pread().
> 
> > +		msr_highest_perf &= (1ULL << 8) - 1;
> 
> 0x771 and the 8-bit mask are magic numbers. Named defines would
> help readability, e.g.:
> 
>   #define MSR_HWP_CAPABILITIES  0x771
>   #define HIGHEST_PERF_MASK     0xFF
> 
> The test fails because msr device is not available, so you need:
> 
>   .needs_drivers = (const char *const [])
> {                                                                    
>                                     
>      
> "msr",                                                               
>                                                                      
>    
>      
> NULL                                                                 
>                                                                      
>    
>   },
> 
> And probably the CONFIG_X86_MSR=y check as well.
> 
> Regards,
> --
> Andrea Cervesato
> SUSE QE Automation Engineer Linux
> andrea.cervesato@suse.com
---------------------------------------------------------------------
Intel Technology Poland sp. z o.o.
ul. Slowackiego 173 | 80-298 Gdansk | Sad Rejonowy Gdansk Polnoc | VII Wydzial Gospodarczy Krajowego Rejestru Sadowego - KRS 101882 | NIP 957-07-52-316 | Kapital zakladowy 200.000 PLN.
Spolka oswiadcza, ze posiada status duzego przedsiebiorcy w rozumieniu ustawy z dnia 8 marca 2013 r. o przeciwdzialaniu nadmiernym opoznieniom w transakcjach handlowych.

Ta wiadomosc wraz z zalacznikami jest przeznaczona dla okreslonego adresata i moze zawierac informacje poufne. W razie przypadkowego otrzymania tej wiadomosci, prosimy o powiadomienie nadawcy oraz trwale jej usuniecie; jakiekolwiek przegladanie lub rozpowszechnianie jest zabronione.
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