[LTP] [PATCH] hugemmap15: Support RISC-V to do __cache_flush. (#79)

[LTP] [PATCH] hugemmap15: Support RISC-V to do __cache_flush. (#79)

[Hui Min Mina Chou via ltp]

AndesCore CPU test fails due to an illegal instruction at the first
jumpfunc(), caused by executing incorrect instructions after
self-modifying code.

On RISC-V CPUs, a FENCE.i synchronizes instruction and data streams,
ensuring that subsequent instruction fetch on a RISC-V hart will see
any previous data stores already visible to the same RISC-V hart.

Thus, cacheflush() in the test should also use __clear_cache for RISC-V.
In SMP systems, it invokes the kernel syscall riscv_flush_icache to inform
each hart to flush their local i-caches.

Signed-off-by: Hui Min Mina Chou <minachou@andestech.com>
---
 testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c b/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
index 4d198407044a..a84ba6476f1e 100644
--- a/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
+++ b/testcases/kernel/mem/hugetlb/hugemmap/hugemmap15.c
@@ -47,7 +47,7 @@ static void cacheflush(void *p)
 {
 #if defined(__powerpc__)
 	asm volatile("dcbst 0,%0; sync; icbi 0,%0; isync" : : "r"(p));
-#elif defined(__arm__) || defined(__aarch64__)
+#elif defined(__arm__) || defined(__aarch64__) || defined(__riscv)
 	__clear_cache(p, p + COPY_SIZE);
 #else
 	(void)p;
-- 
2.34.1


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Re: [LTP] [PATCH] hugemmap15: Support RISC-V to do __cache_flush. (#79)

[Petr Vorel]

Hi Hui,

> AndesCore CPU test fails due to an illegal instruction at the first
> jumpfunc(), caused by executing incorrect instructions after
> self-modifying code.

> On RISC-V CPUs, a FENCE.i synchronizes instruction and data streams,
> ensuring that subsequent instruction fetch on a RISC-V hart will see
> any previous data stores already visible to the same RISC-V hart.

> Thus, cacheflush() in the test should also use __clear_cache for RISC-V.
> In SMP systems, it invokes the kernel syscall riscv_flush_icache to inform
> each hart to flush their local i-caches.

Reviewed-by: Petr Vorel <pvorel@suse.cz>

BTW what "#79" in the git message subject means?

Kind regards,
Petr

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Re: [LTP] [PATCH] hugemmap15: Support RISC-V to do __cache_flush.

[Mina Chou via ltp]

On Thu, May 09, 2024 at 10:06:49AM +0200, Petr Vorel wrote:
> [EXTERNAL MAIL]
> 
> Hi Hui,
> 
> > AndesCore CPU test fails due to an illegal instruction at the first
> > jumpfunc(), caused by executing incorrect instructions after
> > self-modifying code.
> 
> > On RISC-V CPUs, a FENCE.i synchronizes instruction and data streams,
> > ensuring that subsequent instruction fetch on a RISC-V hart will see
> > any previous data stores already visible to the same RISC-V hart.
> 
> > Thus, cacheflush() in the test should also use __clear_cache for RISC-V.
> > In SMP systems, it invokes the kernel syscall riscv_flush_icache to inform
> > each hart to flush their local i-caches.
> 
> Reviewed-by: Petr Vorel <pvorel@suse.cz>
> 
> BTW what "#79" in the git message subject means?
> 
> Kind regards,
> Petr
Hi Petr,

Sorry, that was my mistake. I'll remove it and send another one.

Thanks,
Mina

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