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Thu, 14 Dec 2023 02:09:43 -0800 (PST) Received: from thinkpad ([117.216.120.87]) by smtp.gmail.com with ESMTPSA id ca40-20020a056a0206a800b005897bfc2ed3sm9703702pgb.93.2023.12.14.02.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Dec 2023 02:09:42 -0800 (PST) Date: Thu, 14 Dec 2023 15:39:36 +0530 From: Manivannan Sadhasivam To: Krishna Chaitanya Chundru Cc: lpieralisi@kernel.org, kw@linux.com, kishon@kernel.org, bhelgaas@google.com, mhi@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 6/9] PCI: epf-mhi: Enable MHI async read/write support Message-ID: <20231214100936.GI2938@thinkpad> References: <20231127124529.78203-1-manivannan.sadhasivam@linaro.org> <20231127124529.78203-7-manivannan.sadhasivam@linaro.org> Precedence: bulk X-Mailing-List: mhi@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, Dec 14, 2023 at 03:10:01PM +0530, Krishna Chaitanya Chundru wrote: > > On 11/27/2023 6:15 PM, Manivannan Sadhasivam wrote: > > Now that both eDMA and iATU are prepared to support async transfer, let's > > enable MHI async read/write by supplying the relevant callbacks. > > > > In the absence of eDMA, iATU will be used for both sync and async > > operations. > > > > Signed-off-by: Manivannan Sadhasivam > > --- > > drivers/pci/endpoint/functions/pci-epf-mhi.c | 7 ++++--- > > 1 file changed, 4 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c > > index 3d09a37e5f7c..d3d6a1054036 100644 > > --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c > > +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c > > @@ -766,12 +766,13 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) > > mhi_cntrl->raise_irq = pci_epf_mhi_raise_irq; > > mhi_cntrl->alloc_map = pci_epf_mhi_alloc_map; > > mhi_cntrl->unmap_free = pci_epf_mhi_unmap_free; > > + mhi_cntrl->read_sync = mhi_cntrl->read_async = pci_epf_mhi_iatu_read; > > + mhi_cntrl->write_sync = mhi_cntrl->write_async = pci_epf_mhi_iatu_write; > > if (info->flags & MHI_EPF_USE_DMA) { > > mhi_cntrl->read_sync = pci_epf_mhi_edma_read; > > mhi_cntrl->write_sync = pci_epf_mhi_edma_write; > > - } else { > > - mhi_cntrl->read_sync = pci_epf_mhi_iatu_read; > > - mhi_cntrl->write_sync = pci_epf_mhi_iatu_write; > > + mhi_cntrl->read_async = pci_epf_mhi_edma_read_async; > > + mhi_cntrl->write_async = pci_epf_mhi_edma_write_async; > > I think the read_async & write async should be updated inside the if > condition where MHI_EPF_USE_DMA flag is set. > That's what being done here. Am I missing anything? - Mani > - Krishna Chaitanya. > > > } > > /* Register the MHI EP controller */ -- மணிவண்ணன் சதாசிவம்